CIAN - Conference papers

Current teams :	ACASA ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL
Former team :	Phare

Publications CIAN	2017	2018	2019	2020	2021	2022	2023	Total
Books	0	0	1	0	0	0	0	1
Edited books	0	0	0	0	0	0	0	0
Journal articles	8	9	5	11	9	11	2	55
Book chapters	0	0	0	0	0	1	0	1
Conference papers	8	6	16	13	15	14	1	73
Habilitations	0	0	0	0	0	0	0	0
Theses	2	2	0	1	5	0	3	13

LIP6

H. Adel, M. Dessouky, M.‑M. Louërat, H. Gicquel, H. Haddara : “Foreground Digital Calibration of Non-Linear Errors in Pipelined A/D Converters”, IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, pp. 569-572, (IEEE) [Adel 2010]
M. Agoyan, B. Robisson, M. Nguyen, P. Bazargan‑Sabet, G. Phan, S. Le Henaff : “SOS An innovative secure system architecture”, Cryptarchi, Paris, France [Agoyan 2010a]
M. Agoyan, P. Bazargan Sabet, K. Bekkou, B. Sylvain, S. Le Henaff, E. Lepavec, M. Nguyen, G. Phan, B. Robisson, P. Soquet, F. Wajsbürt : “Smart On Smart”, Colloque « Systèmes embarqués, sécurité et sûreté de fonctionnement », Toulouse, France [Agoyan 2010b]
J.‑M. Akre, J. Juillard, D. Galayko, E. Colinet : “Synchronized State in Networks of Digital Phase-Locked Loops”, 8^th IEEE International NEWCAS Conference (NEWCAS'10), Montreal, Canada, pp. 89-92 [Akre 2010a]
J.‑M. Akre, J. Juillard, S. Olaru, D. Galayko, E. Colinet : “Determination of the Behaviour of Self-Sampled Digital Phase-Locked Loops”, 53rd IEEE International Midwest Symposium on Circuits ans Systems (MWSCAS'10), Seattle, United States, pp. 1089-1092, (IEEE) [Akre 2010b]
M. Allam, H. Aboushady, M.‑M. Louërat : “Continuous-Time ΣΔ modulators with VCO-Based voltage-to-phase and voltage-to-frequency quantizers”, MWSCAS 2010 - Midwest Symposium on Circuits and Systems, Seattle, United States, pp. 676-679, (IEEE) [Allam 2010]
E. Amouri, Z. Marrakchi, H. Mehrez : “Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA”, APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 296-299, (IEEE) [Amouri 2010]
Ah. Ashry, Ahmed K. El‑Shennawy, M. Elbadry, A. Elsayed, H. Aboushady : “Measurement of continuous-time ΣΔ modulators: Implications of using spectrum analyzer”, IEEE International Conference on Microelectronics (ICM'10), Cairo, Egypt, pp. 9-12, (IEEE) [Ashry 2010a]
Ah. Ashry, H. Aboushady : “A generalized approach to design CT ΣΔMs based on FIR DAC”, IEEE International Symposium on Circuits and Systems (ISCAS'10), Paris, France, pp. 21-24, (IEEE) [Ashry 2010b]
Ah. Ashry, H. Aboushady : “Jitter analysis of bandpass continuous-time ΣΔMs for different feedback DAC shapes”, IEEE International Symposium on Circuits and Systems (ISCAS'10), Paris, France, pp. 3997-4000, (IEEE) [Ashry 2010c]
Ah. Ashry, H. Aboushady : “Main Defects of LC-Based ΣΔ Modulators”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'10), Seattle, United States, pp. 897-900 [Ashry 2010d]
Ah. Ashry, H. Aboushady : “Modeling Jitter in Continuous-Time ΣΔ Modulators”, IEEE International Behavioral Modeling and Simulation Conference (BMAS'10), San Jose, CA, United States, pp. 55-58, (IEEE) [Ashry 2010e]
A. Bara, P. Bazargan Sabet, R. Chevallier, E. Encrenaz, D. Le Dû, P. Renault : “Formal Verification of Timed VHDL Programs”, Forum on Specification & Design Languages, FDL 2010, Southampton, United Kingdom, pp. 80-85, (IET) [Bara 2010]
D. Belfort, H. Aboushady : “Automatic Design of RF Linear Transconductor”, LASCAS IEEE Circuits and Systems Society Latin American Symposium on Circuits and Systems, Foz do Iguaçu, Brazil [Belfort 2010]
B. Darvish, P. Bazargan Sabet, P. Renault : “A methodology for Analysis of Voltage Drop in VLSI Digital Circuits”, International Conference on Modeling, Simulation and Control (ICMSC'2010), Cairo, Egypt [Darvish 2010]
U. Farooq, Z. Marrakchi, H. Mehrez : “A New Datapath-Oriented Tree-based FPGA Architecture”, IEEE International Conference on Microelectronics (ICM), Cairo, Egypt, pp. 403-406, (IEEE) [Farooq 2010]
W. Gaber, M. Allam, H. Aboushady, M.‑M. Louërat, E.‑S. Eid : “Systematic design of continuous-time ΣΔ modulator with VCO-based quantizer”, ISCAS 2010 - IEEE International Symposium on Circuits and Systems, Paris, France, pp. 29-32, (IEEE) [Gaber 2010]
R. Guillemet, Ph. Basset, D. Galayko, T. Bourouina : “Combined optimization of electrical and mechanical parameters of an out-of-plane gap-closing electrostatic Vibration Energy Harvester (VEH)”, Symposium on Design Test Integration and Packaging of MEMS/MOEMS (DTIP), Sevilla, Spain, pp. 73-78, (IEEE) [Guillemet 2010a]
R. Guillemet, Ph. Basset, D. Galayko, T. Bourouina : “Combined optimization of electrical and mechanical parameters of in-plane and out-of-plane gap-closing electrostatic Vibration Energy Harvesters (VEHs)”, EUROSENSORS European Conference on sensors, actuators and microsystems, vol. 5, Procedia Engineering, Linz, Austria, pp. 1172-1175, (Elsevier) [Guillemet 2010b]
Z. Guitouni, R. Chotin‑Avot, M. Machhout, H. Mehrez, R. Tourki : “Design and FPGA Implementation of Modular Multiplication Methods Using Cellular Automata”, DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Hammamet, Tunisia, pp. 1-5, (IEEE) [Guitouni 2010]
A. Habib, F. Pêcheux, M.‑M. Louërat : “Systemc-ams modeling of a pcr-ce lab-on-chip for multithreaded dna analysis”, 22^nd International Conference on Microelectronics (ICM), Cairo, Egypt, pp. 483-486, (IEEE) [Habib 2010b]
D. Haghighitalab, M. Vasilevski, H. Aboushady : “LNA automatic synthesis and characterization for accurate RF system-level simulation”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2010), Seattle, WA, United States, pp. 938-941, (IEEE) [Haghighitalab 2010]
F. Hamzaoui, B. Othmani, R. Chotin‑Avot, M. Machhout, H. Belmabrouk, H. Mehrez : “Modélisation et simplification de circuits quantiques”, Materiaux 2010, Mahdia, Tunisia, pp. 2-2 [Hamzaoui 2010]
F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “A Design Environment for Analog IPs Design Knowledge Capture and Migration”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, pp. 1-2 [Javid 2010]
M. Kayal, R. Iskander, R. Castro‑Lopez : “Tutorial Session: Future Trends in Analog EDA”, NEWCAS IEEE International Conference on NEWCAS, Montréal, Québec, Canada [Kayal 2010]
R. Khalil, A. Dudka, D. Galayko, Ph. Basset : “High-voltage low power analogue-to-digital conversion for adaptive architectures of capacitive vibration energy harvesters”, Proceedings of PowerMEMS 2010, Louvain, Belgium, pp. 147-150 [Khalil 2010a]
R. Khalil, A. Dudka, D. Galayko, R. Iskander, Ph. Basset : “Design and Modeling of a Successive Approximation ADC for the Electrostatic Harvester of Vibration Energy”, BMAS 2010 - IEEE International Behavioral Modeling and Simulation Conference, San Jose, United States, pp. 57-62, (IEEE) [Khalil 2010b]
R. Khalil, M. Allam, R. Iskander, M.‑M. Louërat : “Design and Modeling of 8-Bit Successive Approximation Analog to Digital Converter”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, pp. 1-2 [Khalil 2010c]
A. Korniienko, E. Colinet, G. Scorletti, E. Blanco, D. Galayko, J. Juillard : “A clock network of distributed ADPLLs using an asymmetric comparison strategy”, IEEE International Symposium on Circuit and Systems (ISCAS'10), Paris, France, pp. 3212-3215 [Korniienko 2010]
A. Lévêque, F. Pêcheux, M.‑M. Louërat, H. Aboushady, M. Vasilevski : “SystemC-AMS Models for Low-Power Heterogeneous Designs: Application to a WSN for the Detection of Seismic Perturbations”, ARCS '10 - 23^th International Conference on Architecture of Computing Systems, Hannover, Germany, pp. 1-6 [Lévêque 2010]
Z. Marrakchi, H. Parvez, A. Kilic, H. Mehrez, H. Marrakchi : “On the optimization of FPGA area depending on target applications”, APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 308-311, (IEEE) [Marrakchi 2010]
A. Massouri, A. Lévêque, L. Clavier, M. Vasilevski, A. Kaiser, M.‑M. Louërat : “Baseband Fading Channel Simulator for Inter-Vehicle Communication using SystemC-AMS”, 2010 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2010), San Jose, CA, United States, pp. 36-41 [Massouri 2010]
L. Noury, H. Mehrez : “A flexible realtime system for broadband time-frequency analysis in 130 NM CMOS”, ICECS 2010 - 17^th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece, pp. 251-254, (IEEE) [Noury 2010]
H. Parvez, Z. Marrakchi, H. Mehrez : “Application Specific FPGA Using Heterogeneous Logic Blocks”, ARC International Symposium on Applied Reconfigurable Computing, Bangkok, Thailand, pp. 92-109, (Springer) [Parvez 2010a]
H. Parvez, Z. Marrakchi, H. Mehrez : “Heterogeneous-ASIF: An Application Specific Inflexible FPGA using Heterogeneous logic blocks”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, pp. 290-290, (ACM) [Parvez 2010b]
Sabiniano A. Rodrigues, H. Aboushady, M.‑M. Louërat, José I. C. Accioly, Raimundo C. S. Freire : “A Clock-less 8-bit folding A/D converter”, IEEE Latin American Symposium on Circuits and Systems (LASCAS), Foz do Iguacu, Brazil, pp. 25-28, (IEEE) [Rodrigues 2010]
P. Soquet, B. Robisson, M. Agoyan, G. Phan, P. Bazargan Sabet, F. Wajsbürt : “Strategy Of Security on Smart On Smart”, PACA Security Trends In embedded Security, Gardanne, France [Soquet 2010]
M. Turki, M. Abid, Z. Marrakchi, H. Mehrez : “Routability driven placement for mesh-based FPGA architecture”, IDT 2010 - 5^th International Design and Test Workshop, Abu Dhabi, United Arab Emirates, pp. 85-90, (IEEE) [Turki 2010]
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Analog Layout Generation Tool For Nanometer CMOS Technologies”, Colloque national du GDR SOC-SIP, Cergy, France, pp. 1-2 [Youssef 2010a]
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Automatic Stress Effects Computation Based On A Layout Generation Tool For Analog IC”, 2010 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2010), San Jose, CA, United States, pp. 7-12 [Youssef 2010b]
E. Zianbetov, M. Javidan, F. Anceau, D. Galayko, E. Colinet, J. Juillard : “Design and VHDL Modeling of All-Digital PLLs”, 8^th IEEE International NEWCAS Conference (NEWCAS'10), Montreal, Canada, pp. 293-296, (IEEE) [Zianbetov 2010]

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