| Current teams : | ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL |
| Former team : | ACASA |
| Publications ALSOC | 2023 | 2024 | Total |
|---|---|---|---|
| Books | 0 | 0 | 0 |
| Edited books | 0 | 0 | 0 |
| Journal articles | 6 | 1 | 7 |
| Book chapters | 0 | 0 | 0 |
| Conference papers | 9 | 7 | 16 |
| Habilitations | 0 | 0 | 0 |
| Thesis | 3 | 2 | 5 |
- G. Almaless : “ALMOS : un système d'exploitation pour manycores en mémoire partagée cohérente”, 8ème Conférence Française sur les Systèmes d'Exploitation (CFSE'11), Saint-Malo, France [Almaless 2011]
- P. Berthomé, K. Heydemann, X. Kauffmann‑Tourkestansky, J.‑F. Lalande : “Attaques physiques à haut niveau pour le test de la sécurité des cartes à puce”, Journée Sécurité des Systèmes & Sûreté des Logiciels, Saint-Malo, France [Berthomé 2011a]
- P. Berthomé, K. Heydemann, X. Kauffmann‑Tourkestansky, J.‑F. Lalande : “Simulating physical attacks in smart card C codes: the jump attack case”, e-Smart, Nice - Sophia Antipolis, France [Berthomé 2011b]
- O. Gamoudi, N. Drach, K. Heydemann : “Using runtime activity to dynamically filter out inefficient data prefetches”, Euro-Par European Conference on Parallel computing, vol. 6852, Lecture Notes in Computer Science, Bordeaux, France, pp. 338-350, (Springer) [Gamoudi 2011]
- Y. Gendrault, M. Madec, Ch. Lallement, F. Pêcheux, J. Haiech : “Computer-aided design in synthetic biology: A system designer approach”, 4th International Symposium on Applied Sciences in Biomedical and Communication Technologies (ISABEL 2011), Barcelona, Spain [Gendrault 2011a]
- D. Genius, N. Pouillon : “Analyzing Software Inter-Task Communication Channels on a Clustered Shared Memory Multi Processor +System-on-Chip”, International Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, pp. 1-8, (IEEE) [Genius 2011b]
- D. Genius, N. Pouillon : “Monitoring Software Communication Channels on a Shared Memory Multi-Processor System on Chip”, ReCoSoC Reconfigurable Communication-centric SoCs, Montpellier, France, pp. 1-8, (IEEE) [Genius 2011c]
- I. Maïa Pessoa, A. Vieira De Mello, A. Greiner, F. Pêcheux : “Parallel TLM simulation of MPSoC on SMP workstations: Influence of communication locality”, ICM 2010 - 22nd International Conference on Microelectronics, Cairo, Egypt, pp. 359-362 [Maïa Pessoa 2011]
- M. Nguyen, B. Robisson, M. Agoyan, N. Drach : “Low-cost recovery for the code integrity protection in secure embedded processors”, Symposium on Hardware-Oriented Security and Trust (HOST 2011), San Diego, United States, pp. 99-104 [Nguyen 2011]
- J. Porquet, A. Greiner, Ch. Schwarz : “NoC-MPU: A Secure Architecture for Flexible Co-Hosting on Shared Memory MPSoCs”, DATE Design Automation and Test in Europe Conference Grenoble, France, March 2011, Grenoble, France, pp. 591-594, (IEEE) [Porquet 2011]
- B. Robisson, M. Agoyan, S. Bouquet, M. Nguyen, S. Le Henaff, P. Soquet, G. Phan, F. Wajsbürt, P. Bazargan‑Sabet, N. Drach : “Management of the security in smart secure devices”, SSI 2010 - Smart Systems Integration, Dresden, Germany, pp. 1-9 [Robisson 2011a]
- B. Robisson, M. Agoyan, S. Le Henaff, P. Soquet, G. Phan, F. Wajsbürt, P. Bazargan‑Sabet : “Implementation of complex strategies of security in secure embedded systems”, NTMS 2011 - 4th IFIP International Conference on New Technologies, Mobility and Security, Paris, France, pp. 1-5, (IEEE) [Robisson 2011b]
- M. Rosière, J.‑L. Desbarbieux, N. Drach, F. Wajsbürt : “MORPHEO: a high-performance processor generator for a FPGA implementation”, DASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, pp. 1-8, (IEEE) [Rosière 2011]
- L. Zaourar, A. Munier‑Kordon : “Etude du problème de partage de blocs BIST pour le test des mémoires.”, Congrès annuel de la société française de Recherche Opérationnelle et d'Aide à la Décision, Saint Etienne, France [Zaourar 2011a]
- L. Zaourar, A. Wenzel, Y. Kieffer : “A multi-objective optimization for memory BIST sharing using a genetic algorithm”, IEEE International On-Line Testing Symposium, Athens, Greece, pp. 73-78, (IEEE) [Zaourar 2011b]
- L. Zaourar, Y. Kieffer, A. Wenzel : “A Complete methodology for determining memory BIST optimization under wrappers sharing constraints.”, Asia Symposium on Quality Electronic Design, Kuala Lumpur, Malaysia, pp. 46-53, (IEEE) [Zaourar 2011c]
- L. Zaourar, Y. Kieffer, Ch. Aktouf : “A global optimization for scan chain insertion at the RT-level”, IEEE Annual Symposium on VLSI, Chennai, India, pp. 321-322, (IEEE) [Zaourar 2011d]
- Zh. Zhang, D. Refauvelet, A. Greiner, M. Benabdenbi, F. Pêcheux : “Localization of Damaged Resources in NoC Based Shared-Memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure”, The 29th IEEE VLSI Test Symposium (VTS), Dana Point, California, United States [Zhang 2011]