| Current teams : | ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL |
| Former team : | ACASA |
| Publications ALSOC | 2023 | 2024 | Total |
|---|---|---|---|
| Books | 0 | 0 | 0 |
| Edited books | 0 | 0 | 0 |
| Journal articles | 6 | 1 | 7 |
| Book chapters | 0 | 0 | 0 |
| Conference papers | 9 | 7 | 16 |
| Habilitations | 0 | 0 | 0 |
| Thesis | 3 | 2 | 5 |
- I. Augé, F. Pétrot, R. Buchmann, F. Donnet, P. Gomez, E. Faure : “Disydent : un environnement pour la conception de systèmes numériques synchrones”, SCS congrès international de Signaux Circuits et Systèmes, Monastir, Tunisia, pp. 72-77 [Augé 2004a]
- V. Beaudenon, E. Encrenaz : “Utilisation de Diagrammes de Décision de Données pour la Vérification Fonctionnelle de Systèmes Matériels”, MAJECTSTIC 2004 - MAnifestation des JEunes Chercheurs STIC, Calais, France [Beaudenon 2004]
- M. Benabdenbi, A. Greiner, F. Pêcheux, E. Viaud, M. Tuna : “STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores”, DATE 2004 - Design Automation and Test in Europe Conference, Paris, France, pp. 712-713, (IEEE) [Benabdenbi 2004]
- S. Berrayana, E. Faure, D. Genius, F. Pétrot : “Modular on chip multi processor for routing applications”, Euro-Par 2004 - 10th European Conference on Parallel computing, vol. 3149, Lecture Notes in Computer Science, Pise, Italy, pp. 847-855, (Springer) [Berrayana 2004]
- C. Braunstein, E. Encrenaz : “CTL-Property Transformations along an Incremental Design Process”, AVOCS 2004 - 4th International Workshop on Automated Verification of Critical Systems, London, United Kingdom, pp. 263-278 [Braunstein 2004]
- R. Buchmann, A. Greiner, F. Pétrot : “Fast Cycle Accurate Simulation To Simulate Event-Driven Behavior”, ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pp. 37-40, (IEEE) [Buchmann 2004]
- H. Charlery, A. Greiner, E. Encrenaz, L. Mortiez, A. Andriahantenaina : “Using VCI in a on-chip system around SPIN network”, MIXDES Mixed Design of Integrated Circuits and Systems, Szczecin, Poland, pp. 571-576 [Charlery 2004]
- M. Diaby, M. Tuna, J.‑L. Desbarbieux, F. Wajsbürt : “High level synthesis methodology from C to FPGA used for a network protocol communication.”, RSP 2004 - 15th International Workshop on Rapid System Prototyping, Geneva, Switzerland, pp. 103-108, (IEEE) [Diaby 2004]
- M. Dupré, N. Drach, O. Temam : “VHC: Quickly Building an Optimizer for Complex Embedded Architectures”, CGO IEEE/ACM International Symposium on Code Generation and Optimization, San Jose, California, United States, pp. 53-64, (IEEE) [Dupré 2004]
- P. Nguyen‑Tuong, M.‑M. Rosset‑Louërat, A. Greiner : “Guidelines for Designing Smart and Reusable Analog IP Cores”, Sophia Antipolis MicroElectronics Forum (SAME), Sophia Antipolis, France, pp. 1-6 [Nguyen-Tuong 2004a]
- P. Nguyen‑Tuong, M.‑M. Rosset‑Louërat, A. Greiner : “Managing the Shape Function of Analog Devices in a Slicing Tree Floorplan”, Mixed Design of Integrated Circuits and Systems (MIXDES), Szczecin, Poland, pp. 226-229 [Nguyen-Tuong 2004b]
- P. Nguyen‑Tuong, V. Bourguet, L. De Lamarre, M.‑M. Rosset‑Louërat, A. Greiner : “A Language to Design Generators of Analog Functions”, FDL 2004 - Forum on Specification & Design Languages, Lille, France, pp. 30-31 [Nguyen-Tuong 2004c]
- M.‑M. Paget, M.‑C. Nogier, H. Giroire : “Autoevaluation in 8086 assembly language programming”, CALIE 04 : International conference on Computer Aided Learning in Engineering Education, Grenoble, France, pp. 209-214 [Paget 2004]
- M. Tuna, E. Viaud : “STEPS: une approche logicielle pour le test des circuits intégrés sur puce (SoC)”, JNRDM 2004 - 7èmes Journées Nationales du Réseau Doctoral en Microélectronique, Marseille, France, pp. 263-265 [Tuna 2004]