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LIP6 1997/025

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    GenOptim : un environnement d'aide à la conception de générateurs de circuits portables optimisés en performance et en surface
  • A. Houelle
  • 188 pages - 10/16/1997- document en - http://www.lip6.fr/lip6/reports/1997/lip6.1997.025.ps.tar.gz - 2,126 Ko
  • Contact : Alain.Houelle (at) nullasim.lip6.fr
  • Ancien Thème : ASIM
  • In this thesis we investigate the design and implementation of a library of arithmetic operators library. The design of such operators comes to be a very difficult and time consuming task. To get the maximum profit from the development of these operators, it is necessary to maximize their life time which comes to strongly rely on its technological portability. Among all the design methodologies available at time being, the approach based on the standard cell concept offers the best flexibility and ensures a larger portability of the designs. However, the standard cells are more often used in the context of logic synthesis which fails to fully make use of the advantages of this approach. In this thesis there is a proposal of an original design environment for the development of portable arithmetic operators generators based on the standard-cells methodology. This environment allows to benefit from the key advantages of the standard-cells approach and, at the same time increase the range of portability of the architectures. A virtual cell concept has been implemented which makes possible the construction of a netlist without any care of the target library. Moreover, this methodology has been tried to two main issues. The first lies in different placement reconfiguration methods ensuring a better flexibility of the generators to be integrated in a special topological context. The second is a powerful timing optimization tool. This frees the designer from the electrical problems and allows the design of very fast operators. This environment includes high level routines that can be easily used to create the main views needed in VLSI conception. The design methodology presented in this thesis has been successfully used in the design of an image convolution circuit (of about 250 000 transistors) which will be described in detail.
  • Keywords : Technological portability, Standard-Cells, timing optimisations, placement,
    timing analysis, VLSI CAD framework, conception methodology, specific architectures
  • Publisher : Francois.Dromard (at) nulllip6.fr
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