SoC
FOSS for Free HW with a Japanese technology process
Friday, March 9, 2018Naohiko Shimizu, Tokai University
Abstract:``MakeLSI: Project" is a project aiming at realizing an open source Large Scale integration (LSI) design and fabrication community. The project started using the FAIS Semiconductor Center, which is a commonly operated LSI fabrication facility in Kitakyushu, Japan. FAIS offers a 2um, two-metal layer CMOS technology, with a simple and clear lambda-based design rule. Using the PDK does not require signing a NDA and, in addition, the users are free to share and distribute their circuit designs. Finally, the cost to fabricate a wafer is affordable and suitable for training and educational purposes and even for hobbyists.
In order to design the digital part of mixed-signal circuits, the project selected the Alliance OSEDA tool chain from Sorbonne Université-LIP6, and a new open source standard cell library which is based on Alliance included standard cell library. The project has successfully fabricated LSI chips with Alliance using the 180nm, 350nm ROHM technology and the 0.6um Phenitec Semiconductor Corp. technology that will be presented and discussed.
The several benefits that OSEDA and OSHW can offer will be argued and the several difficulties that need to be overcome towards this goal will be pointed out. While several OSEDA and OSHW exist and can be used to perform a low-cost design, it will require a larger collective effort to make OSEDA and OSHW trustful and useful in the context of practical and robust designs.
More details here …
Marie-Minerve.Louerat (at) nulllip6.fr