VALLETTE Farouk

Associate Professor
Team : SYEL
Localisation : Campus Pierre et Marie Curie

Sorbonne Université - LIP6

Tel: +33 1 44 27 84 05, Farouk.Vallette (at) nulllip6.fr

1 PhD graduated 2014

2011-2020 Publications

All Journal articles Conference papers

2020
- M. Terosiet, E. Zianbetov, F. Vallette, M.‑M. Louërat, P. Garda, D. Galayko, S. Feruglio : “A comprehensive in-depth study of tri-state inverter based DCO”, Microelectronics Journal, vol. 99, pp. 104760, (Elsevier) (2020)
2018
- F. Sahel, P. Guilbault, F. Vallette, S. Feruglio : “Impact des bruits d’alimentations et des signaux parasites sur l’intégrité des signaux ultra-rapides”, 13^e Colloque du GDR SoC/SiP, Paris, France (2018)
2016
- R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High-Level Virtual Prototyping of Signal Integrity in Bus Communication”, IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6 (6), pp. 864-872, (Institute of Electrical and Electronics Engineers) (2016)
2015
- O. Tsiakaka, M. Terosiet, O. Romain, A. Histace, H. Benali, P.‑F. Pradat, F. Vallette, M. Feher, S. Feruglio : “In Vivo NIRS Monitoring in Pig Spinal Cord Tissues”, EMBC 2015 - 37^th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Milan, Italy, pp. 4262-4265, (IEEE) (2015)
- O. Tsiakaka, O. Romain, M. Terosiet, A. Histace, H. Benali, P.‑F. Pradat, F. Vallette, A. Alexandre‑Gauthier, M. Feher, S. Feruglio : “Study of the Spinal Cord Activity in the Pig”, 5^es Journées d'Etude sur la TéléSANté (JETSAN), Compiègne, France (2015)
2014
- R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in a USB 3.0 System”, Micro/Nano-Electronics Packaging and Assembly, Design and Manufacturing (MiNaPAD), Grenoble, France (2014)
2013
- R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in a High Frequency Point-to-Point System with SystemC-AMS”, Conference on Design of Circuits and Integrated Systems (DCIS), Donostia-San Sebastian, Spain, pp. 1-4 (2013)
- R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “Modeling of signal integrity in bus communications with timed data flow SystemC-AMS”, FDL 2013 - Forum on Specification Design Languages, Paris, France, pp. 1-6 (2013)
- R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in High Frequency USB 3.0 Systems with SystemC-AMS”, Colloque du GDR Systemes materiels-logiciels integres, Lyon, France (2013)
2012
- R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High level modeling of signal integrity in field bus communication with SystemC-AMS”, Electronics, Circuits and Systems (ICECS), 2012 19^th IEEE International Conference on, Seville, Spain, pp. 889-892 (2012)
- M. Terosiet, S. Feruglio, F. Vallette, D. Galayko, P. Garda : “A Self-Sufficient Digitally Controlled Ring Oscillator Robust to Supply Voltage Fluctuation”, Colloque du GDR SOC-SIP, Paris, France, pp. 1-2 (2012)
- R. Wang, M. Alassir, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “Modeling Field Bus Communication with SystemC-AMS”, Colloque du GDR SOC-SIP, Paris, France, pp. 1-4 (2012)
2011
- M. Terosiet, S. Feruglio, F. Vallette, P. Garda, O. Romain, J. Le Kernec : “A Self-Sufficient Digitally Controlled Ring Oscillator Compensated for Supply Voltage Variation”, The IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Beirut, Lebanon, pp. 484-487, (IEEE) (2011)