MBA Mathieu Leonel

PhD graduated (ATER, Sorbonne Université)
Team : SYEL
    Sorbonne Université - LIP6
    Boîte courrier 169
    Couloir 24-25, Étage 5, Bureau 513
    4 place Jussieu
    75252 PARIS CEDEX 05

Tel: +33 1 44 27 75 07, Mathieu-Leonel.Mba (at)

Supervision : Bertrand GRANADO, Paulin MELATAGIA YONTA

Co-supervision : DENOULET Julien

Automatic generation of distributed hardware platforms for signal processing applications

Local languages or mother tongues of individuals play an essential role in their fulfillment in their various socio-economic activities. African languages and specifically Cameroonian languages are exposed to disappearance in favor of foreign languages adopted as official languages after independence. This is why it is essential to digitalize and integrate them into the majority of dematerialized services for their sustainability. Speech recognition, widely used as a human-machine interface, can be not only a tool for integrating local languages into applications but also a tool for collecting and digitizing corpora. Embedded systems are the preferred environment for deploying applications that use this human-machine interface. This implies that it is necessary to take measures (through the reduction of the reaction time) to satisfy the real-time constraint very often met in this type of application. Two approaches exist for the reduction of the application's response time, namely parallelization and the use of efficient hardware architectures. In this thesis, we exploit a hybrid approach to reduce the response time of an application. We do this by parallelizing this application and implementing it on a reconfigurable architecture. An architecture whose implementation languages are known to be low-level. Moreover, given the multitude of problems posed by the implementation of parallel systems on reconfigurable architecture, there is a problem with design productivity for the engineer. In this thesis, to implement a real-time speech recognition system on an embedded system, we propose an approach for the productive implementation of parallel applications on reconfigurable architecture. Our approach exploits MATIP, a platform-based design tool, as an FPGA Overlay based on high-level synthesis. We exploit this approach to implement a parallel model of a feature extraction algorithm for the recognition of tonal languages (characteristic of the majority of Cameroonian languages). The experimentation of this implementation on isolated words of the Kóló language, in comparison to other implementations (software version and hardware IP), shows that our approach is not only productive in implementation time but also the obtained parallel application is efficient in processing time. This is the reason why we implemented XMATIP an extension of MATIP to make this approach compatible with hardware-software co-design and co-synthesis.

Defence : 09/26/2023

Jury members :

Loïc LAGADEC, Professeur, ENSTA Bretagne [Rapporteur]
Elie FUTE TAGNE, Professeur, Université de Dschang [Rapporteur]
René NDOUNDAM, Professeur, Université de Yaoundé I
Laure GONNORD - Professeur – GrenobleINP/Esisar
Christian GAMOM-Professeur - ENSET, Université de Douala
Maurice TCHUENTE- Professeur Émérite, Université de Yaoundé I
Bertrand GRANADO - Professeur - Sorbonne Université
Paulin MELATAGIA YONTA - Maître de Conférences - Université de Yaoundé I
Julien DENOULET - Maître de Conférences - Sorbonne Université

2022-2023 Publications