IBRAHEEM Mohammed Shaaban

PhD graduated
Team : SYEL
Departure date : 09/30/2017

Supervision : Patrick GARDA

Co-supervision : HACHICHA Khalil

Logarithmic Discrete Wavelet Transform for High-Quality Medical Image Compression

Nowadays, medical image compression is an essential process in eHealth systems. Compressing medical images in high quality is a vital demand to avoid misdiagnosing medical exams by radiologists. WAAVES is a promising medical images compression algorithm based on the discrete wavelet transform (DWT) that achieves a high compression performance compared to the state of the art. The main aims of this work are to enhance image quality when compressing using WAAVES and to provide a high-speed DWT architecture for image compression on embedded systems. Regarding the quality improvement, the logarithmic number systems (LNS) was explored to be used as an alternative to the linear arithmetic in DWT computations. A new LNS library was developed and validated to realize the logarithmic DWT. In addition, a new quantization method called (LNS-Q) based on logarithmic arithmetic was proposed. A novel compression scheme (LNS-WAAVES) based on integrating the Hybrid-DWT and the LNS-Q method with WAAVES was developed. Hybrid-DWT combines the advantages of both the logarithmic and the linear domains leading to enhancement of the image quality and the compression ratio. The results showed that LNS-WAAVES is able to achieve an improvement in the quality by a percentage of 8% and up to 34% compared to WAAVES depending on the compression configuration parameters and the image modalities.
For compression on embedded systems, the major challenge was to design a 2D DWT architecture that achieves a throughput of 100 full HD frame/s. A novel unified 2D DWT computation architecture was proposed. This new architecture performs both horizontal and vertical transform simultaneously and eliminates the problem of column-wise image pixel accesses to/from the off-chip DDR RAM. All of these factors have led to a reduction of the required off-chip DDR RAM bandwidth by more than 2X. The proposed concept uses 4-port line buffers leading to pipelined parallel four operations: the vertical DWT, the horizontal DWT transform, and the read/write operations to the external memory. The proposed architecture has only 1/8 cycles per pixel (CPP) enabling it to process more than 100fps Full HD and it is considered a promising solution for future 4K and 8K video processing. Finally, the developed architecture is highly scalable, outperforms the state of the art existing related work, and currently is deployed in a video EEG medical prototype.

Defence : 03/29/2017 - 14h - Site Jussieu 24-25/405

Jury members :

M. BENSRHAIR Abdelaziz (Université de ROUEN LITIS)
M. LEMIRE Daniel (Université du Québec TELUQ)
Mme. YANG-SONG Fan (Université de Bourgogne UMR CNRS 6306)
M. RABAH Hassan (Université de Lorraine UMR 7198n)
M. Patrick GARDA

2015-2019 Publications