BRIÈRE Alexandre

PhD graduated
Team : SYEL
Departure date : 12/25/2018

Supervision : François PÊCHEUX

Co-supervision : DENOULET Julien

Modélisation système d’une architecture d’interconnexion RF reconfigurable pour les many-cœurs

The growing number of cores in a single chip goes along with an increase in communications. The variety of applications running on the chip causes spatial and temporal heterogeneity of communications. To address these issues, we present in this thesis a dynamically reconfigurable interconnect based on Radio Frequency (RF) for intra chip communications. The use of RF allows to increase the bandwidth while minimizing the latency. Dynamic reconfiguration of the interconnect allows to handle the heterogeneity of communications. We present the rationale for choosing RF over optics and 3D, the detailed architecture of the network and the chip implementing it, the evaluation of its feasibility and its performances. During the evaluation phase we were able to show that for a CMP of 1 024 tiles, our solution allowed a performance gain of 13 %. One advantage of this RF interconnect is the ability to broadcast without additional cost compared to point-to-point communications, opening new perspectives in terms of cache coherence.

Defence : 12/08/2017 - 14h - Campus Jussieu, grande salle de visioconférence, Atrium RdC, porte jaune entrée 2

Jury members :

Dr Fabien Clermidy - CEA - Grenoble [Rapporteur]
Dr Gilles Sassatelli - LIRMM - Montpellier [Rapporteur]
Dr Roselyne Chotin-Avot - UPMC - Paris
Pr Philippe Coussy - UBS - Lorient
Pr Lionel Lacassagne - UPMC - Paris
Pr Ian O’Connor - ECL - Lyon
Dr Julien Denoulet - UPMC - Paris
Pr François Pêcheux - UPMC - Paris

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