SoCRSS

Thermal-Aware Floorplanning


14/11/2017
Intervenant(s) : Iyad OUAISS, Lebanese American University, Beirut, Lebanon (on sabbatical at UPMC)
Power consumption in integrated circuits remains a key problem in VLSI design and excessive temperatures can lead to increased leakage, electromigration, and interference which can greatly affect the operation and performance of a chip. Power reduction is approached at all levels of circuit synthesis and substantial savings can be obtained when optimization techniques are introduced at the behavioral level and when voltage and frequency reductions are allowed. However, time-critical circuits still suffer from temperature rises and floorplanning and placement techniques are required to help alleviate the problem. In this talk, a survey of the thermal problem will be presented along with the different solutions adopted in the literature. The main focus is on physical synthesis and on floorplanning specifically. A two-phase clustering approach is also introduced that benefits from efficient run-times yet helps in preventing the formation of hotspots.
Iyad Ouaiss received his B.S. and Ph.D. degrees in computer engineering from the University of Cincinnati, Cincinnati, Ohio, USA. He joined the Lebanese American University in 2001 and is currently an Associate Professor in the Electrical and Computer Engineering Department. He held several positions in academia and industry. He worked as a Project Engineer in cooperation with the Wright-Patterson Air Force Research Laboratory, and served as Director of the Cisco Institute at the Lebanese American University for several years. His research interests include electronic design automation, VLSI synthesis, reconfigurable computing, high-performance computing, and hardware implementations of signal processing / communications applications.
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