GT PequanRSS

Automating the pipeline of arithmetic datapaths

Intervenant(s) : Matei Istoan (CITI Lab, INSA de Lyon)
The presentation describes the new framework for semi-automatic circuit pipelining that will be used in future releases of FloPoCo, an arithmetic core generator for FPGAs. From a single description of an operator or datapath, optimized implementations can be obtained automatically for a wide range of FPGA targets and a wide range of frequency/latency trade-offs. Compared to previous versions of FloPoCo, the level of abstraction has been raised, enabling easier development, shorter generator code, and better pipeline optimization. The proposed approach is also more flexible than fully automatic pipelining approaches. In the proposed technique, the incremental construction of the pipeline, along with the circuit graph enables architectural design decisions that depend on the pipeline. These allow pipeline-dependent changes to the circuit graph for finer optimization.
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