Prototypage Virtuel partant de transformations de Modèles Haut Niveau : de SysML à SoCLib
Speaker(s) : Daniela Genius
We present a joint framework for validating and exploring complex embedded systems. The framework combines AVATAR, a Model Driven Engineering approach relying on SysML, which is proposed by LabSoc (Telecom ParisTech) with SoCLib, the virtual prototyping platform for multi processor systems-on-chip proposed by ALSOC (Lip6).
Our main contribution lies in the possibility to map AVATAR SysML blocks onto hardware nodes, within a newly conceived Deployment Diagram, and then to transform the latter into SoCLib models.
At the AVATAR level, diagrams can be formally verified and simulated in a functional way only, that is, without considering any underlying hardware execution environment. On the contrary, SocLib models can be simulated taking into account hardware components in an explicit way with a cycle-accurate bit accurate approach. For this simulation, we need to generate semantics preserving code for each AVATAR block, the main program, as well as the top cell and the linker script, taking into account the mapping of blocks and channels defined in the Deployment Diagram.
We present the AVATAR semantics, the code generation for SoCLib, and the way this is supported by our extension to the the TTool toolkit.
The future aim is to develop a Design Space Exploration Environment which is easy to use but exploits the very precise information from cycle accurate simulation.