Séminaire SoCRSS

Leakage Power in Deep Sub-micron Process Technology

Intervenant(s) : Smriti JOSHI (Lip6)
Leakage power has become a top concern for IC designers in deep sub-micron process technology nodes (65nm and below) because it has increased to 30-50% of the total IC power consumption. In addition, the leakage problem is worse than generally thought because the simple, traditional leakage power estimation of multiplying the average transistor leakage by the transistor width of the entire IC grossly underestimates the actual product leakage. That's why statistical leakage estimation, which analytically estimates the leakage-current distribution of a circuit, is a new and promising technique for leakage estimation in the deep-sub micron era.
In this presentation you will come across the predominant physical process parameters for static power consumption variation for a 32nm technology node. Secondly, a new method to create cells leakage correlation matrix and lastly a new gate level statistical leakage estimation methodology to estimate the leakage power consumption of CMOS digital circuits taking into account input states and process variations will be presented for bigger complex circuits in 32nm technology.
Pirouz.Bazargan-Sabet (at) nulllip6.fr
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