Séminaire REGAL


WCET estimation techniques for multicore-processors

Wednesday, September 25, 2013
Speaker(s) : Isabelle Puaut (IRISA)

Hard real-time systems require strict respect of their timing constraints in all execution scenarios, including the worst-case. At the level of a sequential task, worst-case execution times (WCET) have to be determined to demonstrate that task deadlines are met. WCET estimates have to be greater than any possible task execution time (safety property), motivating the use of WCET estimation techniques that use static analysis of the tasks' code. With the advent of multi-core architectures, worst case execution time (WCET) analysis has become an increasingly difficult problem, because multi-core processors employ shared resources (shared cache, shared bus). For instance, the presence of a shared cache requires the modeling of inter-core cache conflicts. In this talk, after a brief presentation of the base static WCET estimation techniques, we will focus on the issues raised by multi-core architectures. Our last work to address these issues will be presented (analysis of interferences for shared caches, hardware support for cache partitioning). An overview of our static WCET estimation tool Heptane will also be given.

Gilles.Muller (at) nulllip6.fr