LIP6 CNRS Sorbonne Université Tremplin Carnot Interfaces
Direct Link LIP6 » Tin tức » Nghiên cứu sinh

GAMOM NGOUNOU EWO Roland Christian

Tiến sĩ
Nhóm nghiên cứu : SYEL
Ngày đi : 31-12-2015
Ban lãnh đạo nghiên cứu : Bertrand GRANADO
Đồng hướng dẫn : FOTSIN Hilaire Bertrand

Déploiement d'applications parallèles sur une architecture distribuée matériellement reconfigurable

Among the architectural targets that could be buid a system on chip (SoC), dynamically reconfigurable architectures (DRA) offer interesting potential for flexibility and dynamicity. However this potential is still difficult to use in massively parallel on chip applications. In our work we identified and analyzed the solutions currently proposed to use DRA and found their limitations including: the use of a particular technology or proprietary architecture, the lack of parallel applications consideration, the difficult scalability, the lack of a common language adopted by the community to use the flexibility of DRA... In our work we propose a solution for deployment on an DRA of a parallel application using standard SoC design flows. This solution is called MATIP ( textit {MPI Application Platform Task Integreation}) and uses primitives of MPI standard Version 2 to make communications and to reconfigure the MP-RSoC architecture . MATIP is a Platform-Based Design (PBD) level solution. The MATIP platform is modeled in three layers: interconnection, communication and application. Each layer is designed to satisfies the requirements of heterogeneity and dynamicity of parallel applications. For this, MATIP uses a distributed memory architecture and utilizes the message passing parallel programming paradigm to enhance scalability of the platform. MATIP frees the designer of all the details related to interconnection, communication between tasks and management of dynamic reconfiguration of the hardware target. A demonstrator of MATIP was performed on Xilinx FPGA through the implementation of an application consisting of two static and two dynamic hardware tasks. MATIP offers a bandwidth of 2.4 Gb/s and latency of 3.43 microseconds for the transfer of a byte. Compared to other MPI platforms (TMD-MPI, SOC-MPI MPI HAL), MATIP is in the state of the art.
Bảo vệ luận án : 22-06-2015 - 14h - Site Jussieu 55-65/211
Hội đồng giám khảo :
Fabrice MULLER, Maître de Conférence, Université Nice Sophia Antipolis, [Rapporteur]
Samy MEFTALI, Maître de Conférences, Université des Sciences et Technologies de Lille (USTL), [Rapporteur]
Bertrand GRANADO, Professeur, UPMC
Hilaire Bertrand FOTSIN, Professeur, Université de Dschang
Sébastien PILLEMENT, Professeur, Ecole polytechnique de l'université de Nantes
Andréa PINNA, Maître de Conférence, Université Pierre et Marie Curie
Benoît MIRAMOND, Maître de Conférence, Université de Cergy Pontoise
Emmanuel CHAILLOUX, Professeur, Université Pierre et Marie Curie

Bài báo khoa học 2015

 Mentions légales
Sơ đồ site |