Associate Professor
Team : ALSOC
Localisation : Campus Pierre et Marie CurieSorbonne Université - LIP6 Boîte courrier 169 Couloir 24-25, Étage 4, Bureau 408 4 place Jussieu 75252 PARIS CEDEX 05 FRANCE Tel: +33 1 44 27 20 38, Emmanuelle.Encrenaz (at) nulllip6.fr http://www-asim.lip6.fr/~ema/
BEN EL OUAHMA Ines : Analyse de robustesse et sécurisation de codes assembleur contre les attaques physiques.
2020
BREJON Jean-Baptiste : Quantification de la sécurité des applications en présence d'attaques physiques et détection de chemins d'attaques.
2014
MORO Nicolas : Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués.
2013
SYED-ALWI Syed-Hussein : Vérification compositionnelle pour la conception sure de systèmes embarqués.
2009
TAKTAK Sami : Détection des interblocages dans les réseaux sur puce.
2007
BRAUNSTEIN Cécile : Conception Incrémentale, Vérification de Composants Matériels et Méthode d'Abstraction pour Vérification de Systèmes Intégrés sur Puce.
2006
BEAUDENON Vincent : Diarammes de décision de données pour la vérification de systemes matériels.
J.‑B. Bréjon, K. Heydemann, E. Encrenaz, Quentin L. Meunier, S. Vu : “Fault attack vulnerability assessment of binary code”, Cryptography and Security in Computing Systems (CS2’19), Valencia, Spain, pp. 13-18, (ACM) (2019)
L. Goubet, K. Heydemann, E. Encrenaz, R. De Keulenaer : “Efficient Design and Evaluation of Countermeasures against Fault Attack with Formal Verification”, Smart Card Research and Advanced Applications - 14th International Conference, CARDIS 2015, Bochum, Germany, November 4-6, 2015. Revised Selected Paper, vol. 9514, Lecture Notes in Computer Science, Bochum, Germany, pp. 177-192, (Springer International Publishing) (2016)
2015
H. Mokrani, R. Ameur‑Boulifa, E. Encrenaz : “Assisting Refinement in System-on-Chip Design”, chapter in Languages, Design Methods, and Tools for Electronic System Design, Selected Contributions from FDL 2013, vol. 311, Lecture Notes in Electrical Engineering, pp. 21-42, (Springer) (2015)
G. Plouviez, E. Encrenaz, F. Wajsbürt : “A formally verified hypervisor with hardware support for a many-core chip”, The 1st Workshop on Runtime and Operating Systems for the Many-core Era, ROME 2013, vol. 8374, Lecture Notes in Computer Science, Aachen, Germany, pp. 801-811, (Springer) (2013)
A. Bara, P. Bazargan Sabet, R. Chevallier, E. Encrenaz, D. Le Dû, P. Renault : “Formal Verification of Timed VHDL Programs”, Forum on Specification & Design Languages, FDL 2010, Southampton, United Kingdom, pp. 80-85, (IET) (2010)
V. Beaudenon, E. Encrenaz, S. Taktak : “Data Decision Diagrams for Promela Systems Analysis”, International Journal on Software Tools for Technology Transfer, vol. 12 (5), pp. 337-352, (Springer Verlag) (2010)
S. Baarir, C. Braunstein, E. Encrenaz, J.‑M. Ilié, T. Li, I. Mounier, D. Poitrenaud, S. Younes : “Quantifying Robustness by Symbolic Model checking”, 1st Hardware Verification Workshop (CAV workshop), Edinburgh, United Kingdom, pp. 1-12 (2010)
É. André, E. Encrenaz, L. Fribourg, Th. Chatain : “An Inverse Method for Parametric Timed Automata”, International Journal of Foundations of Computer Science, vol. 20 (5), pp. 819-836, (World Scientific Publishing) (2009)
S. Baarir, C. Braunstein, R. Clavel, E. Encrenaz, J.‑M. Ilié, R. Leveugle, I. Mounier, L. Pierre, D. Poitrenaud : “Complementary formal approaches for dependability analysis”, The 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Chicago, Illinois, United States, pp. 331-339, (IEEE Computer Society) (2009)
2008
É. André, Th. Chatain, E. Encrenaz, L. Fribourg : “An Inverse Method for Parametric Timed Automata”, Proceedings of the Second Workshop on Reachability Problems in Computational Models (RP 2008), vol. 223, Electronic Notes in Theoretical Computer Science, Liverpool, United Kingdom, pp. 29-46, (Elsevier) (2008)
H. Charlery, A. Greiner, E. Encrenaz, L. Mortiez, A. Andriahantenaina : “Using VCI in a on-chip system around SPIN network”, MIXDES Mixed Design of Integrated Circuits and Systems, Szczecin, Poland, pp. 571-576 (2004)
2003
C. Roux, E. Encrenaz : “CTL May Be Ambiguous When Model Checking Moore Machines”, CHARME 2003 - 12th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, vol. 2860, Lecture Notes in Computer Science, L'Aquila, Italy, pp. 164-169, (Springer) (2003)
V. Beaudenon, E. Encrenaz, J.‑L. Desbarbieux : “Design Validation of ZCSP with SPIN”, IEEE Third International Conference on Application of Concurrency to System Design (ACSD 2003), Guimaraes, Portugal, pp. 102-110, (IEEE) (2003)
J.‑M. Couvreur, E. Encrenaz, E. Paviot‑Adet, D. Poitrenaud, P.‑A. Wacrenier : “Data Decision Diagrams for Petri Net analysis”, 23th International Conference on Application and Theory of Petri Nets, vol. 2360, Lecture Notes in Computer Science, Adelaide, Australia, pp. 101-120, (Springer-Verlag) (2002)
F. Rahim, E. Encrenaz, M. Minoux, Rajesh K. Bawa : “Modular Model Checking of VLSI Designs described in VHDL”, IEEE International Conference on Computer and their Applications, Honolulu, Hawai, United States, pp. 365-368 (1998)