2 PhD students (Supervision / Co-supervision)

• LI Songlin : Modeling of a Smart Medical Implant in its environment for the spinal cord functional monitoring
• SAHEL Faten : Bruit d'alimentations et signaux parasites intrinsèques dans les circuits imprimés à forte densité et forte puissance, impact sur l'intégrité du signal des circuits mixtes ultra rapides.

2 PhD graduated 2014 - 2018

2006-2020 Publications

• 2020
  • O. Tsiakaka, B. Gosselin, S. Feruglio : “Source–Detector Spectral Pairing-Related Inaccuracies in Pulse Oximetry: Evaluation of the Wavelength Shift”, Sensors, vol. 20 (11), pp. 3302, (MDPI) (2020)
  • M. Terosiet, E. Zianbetov, F. Vallette, M.‑M. Louërat, P. Garda, D. Galayko, S. Feruglio : “A comprehensive in-depth study of tri-state inverter based DCO”, Microelectronics Journal, vol. 99, pp. 104760, (Elsevier) (2020)
• 2018
  • S. Feruglio : “Du composant au système hétérogène en environnement contraint : Contribution à la réalisation et à la modélisation de dispositifs embarqués robustes”, habilitation, defence 01/29/2018 (2018)
  • F. Sahel, P. Guilbault, F. Vallette, S. Feruglio : “Impact des bruits d’alimentations et des signaux parasites sur l’intégrité des signaux ultra-rapides”, 13^e Colloque du GDR SoC/SiP, Paris, France (2018)
  • S. Feruglio, O. Tsiakaka : “Toward the monitoring of the spinal cord: A feasibility study”, Microelectronics Journal, (Elsevier) (2018)
• 2016
  • O. Tsiakaka, M. Terosiet, O. Romain, H. Benali, V. Marchand, P. F. Pradat, S. Feruglio : “SpinalCOM: Ambulatory monitoring of the Spinal Cord”, Colloque du GDR SoC-SiP, Nantes, France (2016)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High-Level Virtual Prototyping of Signal Integrity in Bus Communication”, IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6 (6), pp. 864-872, (Institute of Electrical and Electronics Engineers) (2016)
  • S. Feruglio, Th. Courcier, O. Tsiakaka, A. Karami, A. Alexandre‑Gauthier, O. Romain, V. Aimez, Paul G. Charette, P. Pittet, G.‑N. Lu : “A CMOS Buried Quad p-n Junction Photodetector Model”, IEEE Sensors Journal, vol. 16 (6), pp. 1611-1620, (Institute of Electrical and Electronics Engineers) (2016)
• 2015
  • O. Tsiakaka, M. Terosiet, O. Romain, A. Histace, H. Benali, P.‑F. Pradat, F. Vallette, M. Feher, S. Feruglio : “In Vivo NIRS Monitoring in Pig Spinal Cord Tissues”, EMBC 2015 - 37^th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Milan, Italy, pp. 4262-4265, (IEEE) (2015)
  • I. Zbierska, L. Militaru, F. Calmon, S. Feruglio, G.‑N. Lu : “Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET”, Microelectronics Journal, vol. 46 (7), pp. 588-592, (Elsevier) (2015)
  • O. Tsiakaka, O. Romain, M. Terosiet, A. Histace, H. Benali, P.‑F. Pradat, F. Vallette, A. Alexandre‑Gauthier, M. Feher, S. Feruglio : “Study of the Spinal Cord Activity in the Pig”, 5^es Journées d'Etude sur la TéléSANté (JETSAN), Compiègne, France (2015)
  • G.‑N. Lu, Th. Courcier, B. Mamdy, S. Feruglio, P. Charette, V. Aimez, O. Romain, P. Pittet : “CMOS buried multi-junction (BMJ) detector for bio-chemical analysis”, Applied Optics and Photonics China (AOPC), Beijing, China, pp. 1-6, (SPIE) (2015)
  • O. Tsiakaka, O. Romain, H. Benali, P.‑F. Pradat, S. Feruglio : “Imaging of Haemodynamic Spinal Cord Activity in the Pig”, 7^th International IEEE EMBS Neural Engineering Conference, Montpellier, France (2015)
• 2014
  • I. Zbierska, L. Militaru, F. Calmon, S. Feruglio, G.‑N. Lu : “Investigation of Electrical Characteristics of Multi-Gate Bulk nMOSFET”, Microelectronics Proceedings - MIEL 2014, 2014 29^th International Conference on, Belgrade, Serbia, pp. 95-98 (2014)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in a USB 3.0 System”, Micro/Nano-Electronics Packaging and Assembly, Design and Manufacturing (MiNaPAD), Grenoble, France (2014)
  • S. Feruglio, Th. Courcier, A. Karami, A. Alexandre‑Gauthier, O. Romain, V. Aimez, P. Charette, P. Pittet, G.‑N. Lu : “Opto-electrical Modeling of CMOS Buried Quad Junction Photodetector”, Key Engineering Materials, vol. 605, pp. 470-473, (Trans Tech Publications) (2014)
• 2013
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in a High Frequency Point-to-Point System with SystemC-AMS”, Conference on Design of Circuits and Integrated Systems (DCIS), Donostia-San Sebastian, Spain, pp. 1-4 (2013)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “Modeling of signal integrity in bus communications with timed data flow SystemC-AMS”, FDL 2013 - Forum on Specification Design Languages, Paris, France, pp. 1-6 (2013)
  • I. Zbierska, L. Militaru, F. Calmon, S. Feruglio, G.‑N. Lu : “Experimental Study of a Bulk-Technology Tri-gates nMOSFET”, Colloque du GDR Systemes materiels-logiciels integres, Lyon, France (2013)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in High Frequency USB 3.0 Systems with SystemC-AMS”, Colloque du GDR Systemes materiels-logiciels integres, Lyon, France (2013)
• 2012
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High level modeling of signal integrity in field bus communication with SystemC-AMS”, Electronics, Circuits and Systems (ICECS), 2012 19^th IEEE International Conference on, Seville, Spain, pp. 889-892 (2012)
  • M. Terosiet, S. Feruglio, F. Vallette, D. Galayko, P. Garda : “A Self-Sufficient Digitally Controlled Ring Oscillator Robust to Supply Voltage Fluctuation”, Colloque du GDR SOC-SIP, Paris, France, pp. 1-2 (2012)
  • R. Wang, M. Alassir, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “Modeling Field Bus Communication with SystemC-AMS”, Colloque du GDR SOC-SIP, Paris, France, pp. 1-4 (2012)
• 2011
  • M. Terosiet, S. Feruglio, D. Galayko, P. Garda : “An analytical model of the oscillation period for tri-state inverter based DCO”, Microelectronics (ICM), 2011 International Conference on, Hammamet, Tunisia (2011)
  • Ch. Shan, E. Zianbetov, M. Javidan, F. Anceau, M. Terosiet, S. Feruglio, D. Galayko, O. Romain, E. Colinet, J. Juillard : “FPGA implementation of reconfigurable ADPLL network for distributed clock generation”, FTP 2011 - International Conference on Field Programmable Technology, New Delhi, India, pp. 1-4, (IEEE) (2011)
  • M. Terosiet, S. Feruglio, F. Vallette, P. Garda, O. Romain, J. Le Kernec : “A Self-Sufficient Digitally Controlled Ring Oscillator Compensated for Supply Voltage Variation”, The IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Beirut, Lebanon, pp. 484-487, (IEEE) (2011)
• 2009
  • S. Feruglio, F. Andrieu, F. Olivier, G. Ghibaudo : “Low-Temperature Electrical Characterization of Fully Depleted eXtra-strained SOI n-MOSFETs with TiN/HfO2 Gate Stack for the 32-nm Technology Node”, Cryogenics, vol. 49 (11), pp. 605-610, (Elsevier) (2009)
  • M. Terosiet, D. Galayko, S. Feruglio : “Bruit dans les oscillateurs contrôlés, application à un réseau de PLLs couplée”, Colloque du GDR SOC-SIP, Orsay, France, pp. 1-2 (2009)
• 2006
  • A. Alexandre, P. Garda, G. Vasilescu, S. Feruglio, A. Pinna, C. Chay, O. Llopis, B. Granado : “Noise Characterization of CMOS Image Sensors”, 10^th WSEAS CSCC n°ISSN 1760-5117, Athens, Greece, pp. 10-15 (2006)