1 Doctorant (Direction de recherche / Co-encadrement)

• TSIAKAKA Olivier : Contribution à la réalisation d'un implant pour l'imagerie chronique de la moëlle épinière.

1 Docteur 2014

Publications 2006-2016

• 2016
  • S. Feruglio, Th. Courcier, O. Tsiakaka, A. Karami, A. Alexandre‑Gauthier, O. Romain, V. Aimez, Paul G. Charette, P. Pittet, G.‑N. Lu : “A CMOS Buried Quad p-n Junction Photodetector Model”, IEEE Sensors Journal, vol. 16 (6), pp. 1611-1620, (ISBN: 1530-437X) (2016)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High-Level Virtual Prototyping of Signal Integrity in Bus Communication”, IEEE Transactions on Components Packaging and Manufacturing Technology, vol. 6 (6), pp. 864-872 (2016)
  • O. Tsiakaka, M. TEROSIET, O. Romain, H. Benali, V. Marchand, P. F. Pradat, S. Feruglio : “SpinalCOM: Ambulatory monitoring of the Spinal Cord”, Colloque du GDR SoC-SiP, Nantes, France (2016)
• 2015
  • I. Zbierska, L. Militaru, F. Calmon, S. Feruglio, G.‑N. Lu : “Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET”, Microelectronics Journal, vol. 46 (7), pp. 588-592, (ISBN: 0026-2692) (2015)
  • G.‑N. Lu, Th. Courcier, B. Mamdy, S. Feruglio, Paul G. Charette, V. Aimez, O. Romain, P. Pittet : “CMOS buried multi-junction (BMJ) detector for bio-chemical analysis”, Applied Optics and Photonics China (AOPC), Beijing, China, pp. 1-6, (SPIE) (2015)
  • O. Tsiakaka, O. Romain, H. Benali, P.‑F. Pradat, S. Feruglio : “Imaging of Haemodynamic Spinal Cord Activity in the Pig”, 7^th International IEEE EMBS Neural Engineering Conference, Montpellier, France (2015)
  • O. Tsiakaka, M. Terosiet, O. Romain, A. Histace, H. Benali, P.‑F. Pradat, F. Vallette, M. Feher, S. Feruglio : “In Vivo NIRS Monitoring in Pig Spinal Cord Tissues”, EMBC 2015 - 37^th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Milan, Italy, pp. 4262-4265, (IEEE) (2015)
  • O. Tsiakaka, O. Romain, M. Terosiet, A. Histace, H. Benali, P.‑F. Pradat, F. Vallette, A. Alexandre‑Gauthier, M. Feher, S. Feruglio : “Study of the Spinal Cord Activity in the Pig”, 5èmes Journées d'Etude sur la TéléSANté (JETSAN), Compiègne, France (2015)
• 2014
  • S. Feruglio, Th. Courcier, A. Karami, A. Alexandre‑Gauthier, O. Romain, V. Aimez, Paul G. Charette, P. Pittet, G.‑N. Lu : “Opto-electrical Modeling of CMOS Buried Quad Junction Photodetector”, Key Engineering Materials, vol. 605, Prague, République Tchèque, pp. 470-473, (Trans Tech Publications, Switzerland) (2014)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in a USB 3.0 System”, Micro/Nano-Electronics Packaging and Assembly, Design and Manufacturing (MiNaPAD), Grenoble, France (2014)
  • I. Zbierska, L. Militaru, F. Calmon, S. Feruglio, G.‑N. Lu : “Investigation of Electrical Characteristics of Multi-Gate Bulk nMOSFET”, 29^th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), Belgrade, Serbia, pp. 95-98, (IEEE) (2014)
• 2013
  • I. Zbierska, L. Militaru, F. Calmon, S. Feruglio, G.‑N. Lu : “Experimental Study of a Bulk-Technology Tri-gates nMOSFET”, Colloque du GDR Systemes materiels-logiciels integres, Lyon, France (2013)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in a High Frequency Point-to-Point System with SystemC-AMS”, Conference on Design of Circuits and Integrated Systems (DCIS), Donostia-San Sebastian, Spain, pp. 1-4 (2013)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in High Frequency USB 3.0 Systems with SystemC-AMS”, Colloque du GDR Systemes materiels-logiciels integres, Lyon, France (2013)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “Modeling of Signal Integrity in Bus Communications with Timed Data Flow SystemC-AMS”, FDL 2013 - Forum on Specification Design Languages, Paris, France, pp. 1-6, (ISBN: 1636-9874) (2013)
• 2012
  • M. Terosiet, S. Feruglio, F. Vallette, D. Galayko, P. Garda : “A Self-Sufficient Digitally Controlled Ring Oscillator Robust to Supply Voltage Fluctuation”, Colloque du GDR SOC-SIP, Paris, France, pp. 1-2 (2012)
  • R. Wang, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “High Level Modeling of Signal Integrity in Field Bus Communication with SystemC-AMS”, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Seville, Spain, pp. 889-892, (IEEE), (ISBN: 978-1-4673-1261-5) (2012)
  • R. Wang, M. Alassir, J. Denoulet, S. Feruglio, F. Vallette, P. Garda : “Modeling Field Bus Communication with SystemC-AMS”, Colloque du GDR SOC-SIP, Paris, France, pp. 1-4 (2012)
• 2011
  • M. Terosiet, S. Feruglio, F. Vallette, P. Garda, O. Romain, J. Le Kernec : “A Self-Sufficient Digitally Controlled Ring Oscillator Compensated for Supply Voltage Variation”, The IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Beirut, Lebanon, pp. 484-487, (IEEE), (ISBN: 978-1-4577-1845-8) (2011)
  • M. Terosiet, S. Feruglio, D. Galayko, P. Garda : “An Analytical Model Of The Oscillation Period For Tri-State Inverter Based DCO”, Microelectronics (ICM), 2011 International Conference on, Hammamet, Tunisia, (IEEE), (ISBN: 978-1-4577-2207-3) (2011)
  • Ch. Shan, E. Zianbetov, M. Javidan, F. Anceau, M. Terosiet, S. Feruglio, D. Galayko, O. Romain, É. Colinet, J. Juillard : “FPGA Implementation of Reconfigurable ADPLL Network for Distributed Clock Generation”, FTP 2011 - International Conference on Field Programmable Technology, New Delhi, India, pp. 1-4, (IEEE), (ISBN: 978-1-4577-1741-3) (2011)
• 2009
  • S. Feruglio, F. Andrieu, F. Olivier, G. Ghibaudo : “Low-Temperature Electrical Characterization of Fully Depleted eXtra-strained SOI n-MOSFETs with TiN/HfO2 Gate Stack for the 32-nm Technology Node”, Cryogenics, vol. 49 (11), pp. 605-610, (ISBN: 0011-2275) (2009)
  • M. Terosiet, D. Galayko, S. Feruglio : “Bruit dans les oscillateurs contrôlés, application à un réseau de PLLs couplée”, Colloque du GDR SOC-SIP, Orsay, France, pp. 1-2 (2009)
• 2008
  • S. Feruglio, G.‑N. Lu, P. Garda, G. Vasilescu : “A Review of CMOS Buried Double Junction (BDJ) Photodetector and its Applications”, Sensors, vol. 8, pp. 6566-6594, (ISBN: 1424-8220) (2008)
  • S. Feruglio, F. Andrieu, F. Olivier, G. Ghibaudo : “In-depth Electrical Characterization of Sub-45nm Full Depleted Strained SOI MOSFETs with TiN/HfO2 Gate Stack”, Solid State Electronics, vol. 52, pp. 489-497 (2008)
  • S. Feruglio, F. Andrieu, F. Olivier, G. Ghibaudo : “Low-Temperature Electrical Characterization of eXtra-strained FD-SOI n-MOSFETs with TiN/HfO2 Gate Stack for the 32 nm Technology Node”, The 8^th International Workshop On Low Temperature Electronics (WOLTE'08), Ilmenau, Germany, pp. 605-610 (2008)
• 2007
  • S. Feruglio, F. Andrieu, F. Olivier, G. Ghibaudo : “Detailed Electrical Characterization of sub 45nm strained FD-SOI c-MOSFETs with TiN/HfO2 gate stack”, The 8^th International Conference on Ultimate Integration on Silicon (ULIS’07), Leuven, Belgium, pp. 1-4 (2007)
  • F. Andrieu, F. Olivier, F. Rochette, J.‑Ch. Barbé, Ch. Buj, Y. Bogumilowicz, F. Allain, V. Delaye, D. Lafond, F. Aussenac, S. Feruglio, J. Eymery, T. Akatsu, P. Maury, L. Brévard, L. Tosti, H. Dansas, E. Rouchouze, J.‑M. Hartmann, L. Vandroux : “Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of 100 or 110 oriented FDSOI cMOSFETs for the 32nm Node”, The 2007 Symposium on VLSI Technology, Kyoto, Japan, pp. 50-51, (ISBN: 978-4-900784-03-1) (2007)
• 2006
  • S. Feruglio, A. Pinna, O. Llopis, C. Chay, B. Granado, A. Alexandre, P. Garda, G. Vasilescu : “Noise Characterization in a CMOS 0.6-ìm PPS Image Sensors System”, WSEAS Transaction on Circuits and Systems, vol. 5, pp. 877-886, (ISBN: 1109-2734) (2006)