LIP6 2002/023
- Thesis
Conception en vue du test de systèmes intégrés sur silicium (SoC) - M. Benabdenbi
- 134 pages - 09/27/2002- document en - http://www.lip6.fr/lip6/reports/2002/lip6.2002.023.pdf - 1,724 Ko
- Contact : Mounir.Benabdenbi (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : SoC, DFT, TAM, wrapper, P1500, IP cores
- Publisher : Francois.Dromard (at) nulllip6.fr
While geometry shrinking and design reuse allow impressive gains, System on a Chip (SoC) testing faces new set of problems and has become one of the bottlenecks of the IC industry progress. As System on a Chip cannot be tested as System on a Board (SoB), some new test architectures must be developed. This thesis describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features. This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundary Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation. These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A toolbox environment is provided, in order to automatically generate the needed components to build the chosen SoC test architecture. Some experimental results are presented for each architecture. A first evaluation of the CAS-BUS TAM applied to a SoC benchmark is also described in this document.