Publications 2004-2016

• 2016
  • S. Chtourou, Z. Marrakchi, E. Amouri, V. Pangracious, M. Abid, H. Mehrez : “Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 40, pp. 16-26, (Elsevier) (2016)
  • S. Chtourou, M. Abid, Z. Marrakchi, E. Amouri, H. Mehrez : “The effect of interconnect depopulation on FPGA performances in terms of power, area and delay”, HPCS 2016 - International Conference on High Performance Computing & Simulation, Innsbruck, Austria, pp. 104-111, (IEEE) (2016)
  • S. Chtourou, Z. Marrakchi, E. Amouri, V. Pangracious, H. Mehrez, M. Abid : “Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance”, PDP 2016 - 24^th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, Heraklion, Crete, Greece, pp. 635-642, (IEEE Computer Society) (2016)
• 2015
  • M. Turki, Z. Marrakchi, H. Mehrez, M. Abid : “Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform”, Design Automation for Embedded Systems, vol. 19 (3), pp. 223-242, (Springer Verlag) (2015)
  • S. Chtourou, Z. Marrakchi, V. Pangracious, E. Amouri, H. Mehrez, M. Abid : “Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization”, ARC 2015 - 11^th International Symposium on Applied Reconfigurable Computing, vol. 9040, Lecture Notes in Computer Science, Bochum, Germany, pp. 411-418, (Springer) (2015)
  • V. Pangracious, Z. Marrakchi, H. Mehrez : “Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA”, IEEE Micro, vol. 35 (6), pp. 48-59, (Institute of Electrical and Electronics Engineers) (2015)
  • N. Belhadj, N. Bahri, Z. Marrakchi, M. Ayed, N. Masmoudi, H. Mehrez : “H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture”, IET Computers & Digital Techniques, vol. 9 (5), pp. 259-267, (Institution of Engineering and Technology) (2015)
  • V. Pangracious, Z. Marrakchi, H. Mehrez : “Three-Dimensional Design Methodologies for Tree-based FPGA Architecture”, vol. 350, Lecture Notes in Electrical Engineering, (Springer), (ISBN: 978-3-319-19173-7) (2015)
• 2014
  • S.‑U. Rehman, A. Blanchardon, A. Ben Dhia, M. Benabdenbi, R. Chotin‑Avot, L. Naviner, L. Anghel, H. Mehrez, E. Amouri, Z. Marrakchi : “Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Tampa, FL, United States, pp. 553-558, (IEEE) (2014)
  • V. Pangracious, E. Amouri, Z. Marrakchi, H. Mehrez : “Architecture level optimization of 3-dimensional tree-based FPGA”, Microelectronics Journal, vol. 45 (4), pp. 355-366, (Elsevier) (2014)
  • N. Belhadj, Z. Marrakchi, M. Ben ayed, N. Masmoudi, H. Mehrez : “MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder”, International Journal of Embedded and Real-Time Communication Systems, vol. 5 (2), pp. 43-60, (IGI Global) (2014)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, Z. Marrakchi, H. Mehrez, Q. Tang : “Towards high performance GHASH for pipelined AES-GCM using FPGAs”, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, United States, pp. 242-242, (ACM) (2014)
  • S. Chtourou, M. Abid, V. Pangracious, E. Amouri, Z. Marrakchi, H. Mehrez : “Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation”, 3DIC 2014 - 2014 International 3D Systems Integration Conference, Kinsdale, Ireland, pp. 1-7, (IEEE) (2014)
  • A. Obeid, S. Qasim, Mohammed S. BenSaleh, Z. Marrakchi, H. Mehrez, H. Ghariani, M. Abid : “Flexible reconfigurable architecture for DSP applications”, SOCC 2014 - 27^th IEEE International System-on-Chip Conference, Las Vegas, NV, United States, pp. 204-209, (IEEE) (2014)
  • V. Pangracious, M. Marrakchi, H. Mehrez, Z. Marrakchi : “On wiring delays reduction of tree-based FPGA using 3-D fabric”, SOCC 2014 - 27^th IEEE International System-on-Chip Conference, Las Vegas, NV, United States, pp. 64-69, (IEEE) (2014)
  • V. Pangracious, Z. Marrakchi, N. Beltaief, H. Mehrez, U. Farooq : “Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA”, DTIS 2014 - 9^th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini, Greece, pp. 1-6, (IEEE) (2014)
  • S. Chtourou, M. Abid, Z. Marrakchi, H. Mehrez : “Power consumption analysis for mesh based FPGA”, DTIS 2014 - 9^th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini, Greece, pp. 1-5, (IEEE) (2014)
  • A. Kilic, Z. Marrakchi, H. Mehrez : “A Top-Down Optimization Methodology for Mutually Exclusive Applications”, International Journal of Reconfigurable Computing, vol. 2014, pp. 827613:1-827613:18, (Hindawi Publishing Corporation) (2014)
• 2013
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology”, IEEE International 3D Systems Integration Conference (3DIC), 2013, San Francisco, CA, United States, pp. 1-8, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, U. Farooq, Z. Marrakchi : “High Performance 3-Dimensional Heterogeneous Tree-based FPGA Architectures (HT-FPGA)”, FPGAworld'13 - The 10^th FPGAworld Conference, Stockholm, Sweden, pp. 3:1-3:6, (ACM) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “Designing 3D tree-based FPGA: Interconnect Optimization and Thermal Analysis”, NEWCAS'13 - IEEE 11^th International Conference on New Circuits and Systems, Paris, France, pp. 1-4, (IEEE) (2013)
  • V. Pangracious, E. Amouri, H. Mehrez, Z. Marrakchi : “Physical Design Exploration of 3D Tree-based FPGA Architecture”, GLSVLSI'13 - The 23^rd ACM international conference on Great lakes symposium on VLSI, Paris, France, pp. 335-336, (ACM) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “Architecture Level TSV Count Minimization Methodology for 3D Tree-based FPGA”, Cool Chips XVI, Yokohama, Japan, pp. 1-3, (IEEE) (2013)
  • Q. Tang, M. Tuna, Z. Marrakchi, H. Mehrez : “Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist”, Proceedings of the 9^th International Symposium on Applied Reconfigurable Computing, ARC 2013, vol. 7806, Lecture Notes in Computer Science, Los Angeles, United States, pp. 221, (Springer) (2013)
  • V. Pangracious, Z. Marrakchi, E. Amouri, H. Mehrez : “Performance analysis and optimization of high density tree-based 3d multilevel FPGA”, Reconfigurable Computing: Architectures, Tools and Applications, vol. 7806, Lecture Notes in Computer Science, Los Angeles, CA, United States, pp. 197-209, (Springer) (2013)
  • E. Amouri, A. Blanchardon, R. Chotin‑Avot, H. Mehrez, Z. Marrakchi : “Efficient Multilevel Interconnect Topology for Cluster-based Mesh FPGA Architecture”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2013)
  • A. Ben Dhia, S. Ur Rehman, A. Blanchardon, L. Naviner, M. Benabdenbi, R. Chotin‑Avot, H. Mehrez, E. Amouri, Z. Marrakchi : “A Defect-tolerant Cluster in a Mesh SRAM-based FPGA”, International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, pp. 434-437, (IEEE Computer Society) (2013)
  • V. Pangracious, Z. Marrakchi, H. Mehrez : “Design and optimization of heterogeneous tree-based FPGA using 3D technology”, FPT 2013 - International Conference on Field-Programmable Technology, Kyoto, Japan, pp. 334-337, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, N. Beltaief, Z. Marrakchi, U. Farooq : “Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2013)
  • M. Turki, H. Mehrez, Z. Marrakchi, M. Abid : “Partitioning constraints and signal routing approach for multi-FPGA prototyping platform”, ISSoC 2013 - International Symposium on System on Chip, Tampere, Finland, pp. 1-4, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “TSV count minimization and thermal analysis for 3D Tree-based FPGA”, ICICDT 2013 - International Conference on IC Design & Technology, Pavia, Italy, pp. 223-226, (IEEE) (2013)
  • M. Turki, Z. Marrakchi, H. Mehrez, M. Abid : “Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform”, ARC 2013 - 9^th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, vol. 7806, Lecture Notes in Computer Science, Los Angeles, CA, United States, pp. 210-217, (Springer) (2013)
  • N. Belhadj, N. Bahri, M. Ali Ben Ayed, Z. Marrakchi, H. Mehrez : “Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC”, 2013 10^th International Multi-Conference on Systems, Signals & Devices (SSD), Hammamet, Tunisia, (IEEE) (2013)
  • U. Farooq, H. Parvez, H. Mehrez, Z. Marrakchi : “Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA”, Microelectronics Journal, vol. 44 (12), pp. 1052-1062, (Elsevier) (2013)
  • M. Turki, Z. Marrakchi, H. Mehrez, M. Abid : “Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform”, International Journal of Reconfigurable Computing, vol. 2013, pp. 853510, (Hindawi Publishing Corporation) (2013)
  • E. Amouri, H. Mehrez, Z. Marrakchi : “Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA”, International Journal of Reconfigurable Computing, vol. 2013 (802436), pp. 24, (Hindawi Publishing Corporation) (2013)
• 2012
  • M. Turki, H. Mehrez, Z. Marrakchi : “Multi-FPGA Prototyping Environment: Large Benchmark Generation and Signals Routing”, 2014 International Conference on Reconfigurable computing and FPGA, Cancun, Mexico (2012)
  • U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “A New Heterogeneous Tree-based Application Specific FPGA and Its Comparison with Mesh-based Application Specific FPGA”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 36 (8), pp. 588-605, (Elsevier) (2012)
  • A. Kilic, Z. Marrakchi, M. Tuna, H. Mehrez : “A Logic Sharing Synthesis Tool for Mutually Exclusive Applications”, Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012 7^th International Conference on, Gammarth, Tunisia, pp. 1-6 (2012)
  • U. Farooq, Z. Marrakchi, H. Mehrez : “Tree Based Heterogeneous FPGA Architectures, Application Specific Exploration and Optimization”, (Springer), (ISBN: 978-1-4614-3593-8) (2012)
• 2011
  • H. Parvez, Z. Marrakchi, A. Kilic, H. Mehrez : “Application-Specific FPGA using heterogeneous logic blocks”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 4 (3), pp. 1-24, (ACM) (2011)
  • E. Amouri, Z. Marrakchi, H. Mehrez : “Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA”, 6^th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Montpellier, France, pp. 1-4, (IEEE) (2011)
  • U. Farooq, H. Parvez, E. Amouri, H. Mehrez, Z. Marrakchi : “Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA”, International conference on Design & Technology of Integrated Systems (DTIS), Athens, Greece, pp. 1-6, (IEEE) (2011)
  • U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA”, The 7^th International Symposium on Applied Reconfigurable Computing, vol. 6578, Lecture Notes in Computer Science, Belfast, United Kingdom, pp. 218-229, (Springer) (2011)
  • U. Farooq, H. Parvez, H. Mehrez, Z. Marrakchi : “Exploration of Heterogeneous FPGA Arcrchitectures”, International Journal of Reconfigurable Computing, vol. 2011, pp. 121404, (Hindawi Publishing Corporation) (2011)
• 2010
  • U. Farooq, Z. Marrakchi, H. Mehrez : “A New Datapath-Oriented Tree-based FPGA Architecture”, IEEE International Conference on Microelectronics (ICM), Cairo, Egypt, pp. 403-406, (IEEE) (2010)
  • H. Parvez, Z. Marrakchi, H. Mehrez : “Application Specific FPGA Using Heterogeneous Logic Blocks”, ARC International Symposium on Applied Reconfigurable Computing, Bangkok, Thailand, pp. 92-109, (Springer) (2010)
  • H. Parvez, Z. Marrakchi, H. Mehrez : “Heterogeneous-ASIF: An Application Specific Inflexible FPGA using Heterogeneous logic blocks”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, pp. 290-290, (ACM) (2010)
  • M. Turki, M. Abid, Z. Marrakchi, H. Mehrez : “Routability driven placement for mesh-based FPGA architecture”, IDT 2010 - 5^th International Design and Test Workshop, Abu Dhabi, United Arab Emirates, pp. 85-90, (IEEE) (2010)
  • E. Amouri, Z. Marrakchi, H. Mehrez : “Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA”, APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 296-299, (IEEE) (2010)
  • Z. Marrakchi, H. Parvez, A. Kilic, H. Mehrez, H. Marrakchi : “On the optimization of FPGA area depending on target applications”, APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 308-311, (IEEE) (2010)
• 2009
  • H. Parvez, Z. Marrakchi, H. Mehrez : “ASIF: Application Specific Inflexible FPGA”, ICFPT International Conference on Field-Programmable Technology, Sydney, Australia, pp. 112-119, (IEEE) (2009)
  • Z. Marrakchi, U. Farooq, H. Mrabet, H. Mehrez : “Comparison of Tree-Based and Mesh-Based Coarse-Grained FPGA Architectures”, ICM International Conference on Microelectronics, Marrakech, Morocco, pp. 248-251, (IEEE) (2009)
  • E. Amouri, H. Mrabet, Z. Marrakchi, H. Mehrez : “Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing”, ReConFig International Conference on Reconfigurable Computing and FPGAs 2009, Cancun, Mexico, pp. 201-206, (IEEE) (2009)
  • E. Amouri, H. Mrabet, Z. Marrakchi, H. Mehrez : “Placement and Routing Techniques to Improve Delay Balance of WDDL Netlist in MFPGA”, IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2009, Hammamet, Tunisia, pp. 791-794, (IEEE) (2009)
  • U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “A New Tree-based coarse-grained FPGA Architecture”, IEEE International Conference on PhD. Research in MicroElectronics, PRIME'09, Cork, Ireland, pp. 48-51, (IEEE) (2009)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “FPGA Interconnect Topologies Exploration”, International Journal of Reconfigurable Computing, vol. 2009, pp. 259837, (Hindawi Publishing Corporation) (2009)
• 2008
  • Z. Marrakchi : “Exploration et Optimisation d’Architectures FPGA Arborescentes”, thèse, soutenance 25/11/2008, direction de recherche Mehrez, Habib (2008)
  • H. Parvez, Z. Marrakchi, U. Farooq, H. Mehrez : “A New Coarse-grained FPGA Architecture Exploration Environment”, ICFPT International Conference on Field-Programmable Technology, Taipei, Taiwan, Province of China, pp. 285-288, (IEEE) (2008)
  • H. Mrabet, H. Parvez, Z. Marrakchi, H. Mehrez : “Automatic Layout Generator of Domain Specific FPGA:”, ICM International Conference on Microelectronics, Sharjah, United Arab Emirates, pp. 183-186, (IEEE) (2008)
  • H. Parvez, Z. Marrakchi, H. Mehrez : “Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-grained FPGAs”, ReConFig International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 121-126, (IEEE) (2008)
  • U. Farooq, Z. Marrakchi, H. Mrabet, H. Mehrez : “The Effect of LUT and Cluster Size on a Tree based FPGA Architecture”, ReConFig International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 115-120, (IEEE) (2008)
  • Z. Marrakchi, H. Mrabet, E. Amouri, H. Mehrez : “Efficient Tree Topology for FPGA Interconnect Network”, GLSVLSI ACM Great Lakes Symposium on VLSI, Orlando, Florida, United States, pp. 321-326, (ACM) (2008)
  • Z. Marrakchi, H. Mrabet, Ch. Masson, H. Mehrez : “Performances Comparison between Multilevel Hierarchical and Mesh FPGA Interconnects”, International Journal of Electronics, vol. 95 (3), pp. 275-289, (Taylor & Francis) (2008)
• 2007
  • Z. Marrakchi, H. Mrabet, Ch. Masson, H. Mehrez : “Efficient Mesh of Tree Interconnect for FPGA Architecture”, ICFPT International Conference on Field-Programmable Technology, Kitakyushu, Japan, pp. 269-272, (IEEE) (2007)
  • Z. Marrakchi, H. Mrabet, Ch. Masson, H. Mehrez : “Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances”, NoC ACM/IEEE International Symposium on Networks-on-Chip, Princeton, United States, pp. 243-252, (IEEE) (2007)
  • Z. Marrakchi, H. Mrabet, G. Souffleteau, Ch. Masson, H. Mehrez : “A Routability Driven Partitioning and Detailed Placement Approach for Multilevel Hierarchical FPGA”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Californie, United States, pp. 225-225 (2007)
• 2006
  • H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez : “Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection Structure”, ICCAD IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, United States, pp. 675-679, (IEEE) (2006)
  • H. Mrabet, Z. Marrakchi, H. Mehrez, A. Tissot : “Implementation of Scalable Embedded FPGA for SOC”, DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia, pp. 74-77, (IEEE) (2006)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Performances comparison between Multilevel hierarchical and Mesh FPGA”, DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia, pp. 166-171, (IEEE) (2006)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, pp. 85-88, (IEEE) (2006)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “A new Multilevel Hierarchical MFPGA and its suitable configuration tools”, ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe, Germany, pp. 263-268, (IEEE) (2006)
  • H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez : “A multilevel hierarchical interconnection structure for FPGA”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, pp. 225-225, (ACM) (2006)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Configuration tools for a new multilevel hierarchical FPGA”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, pp. 229-229, (ACM) (2006)
  • H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez, A. Tissot : “Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure”, ReCoSoC 2006 - 2^nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France, pp. 117-123, (Univ. Montpellier II) (2006)
• 2005
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Hierarchical FPGA clustering to improve routability”, PRIME 2005 - IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, vol. 1, Lausanne, Switzerland, pp. 165-168, (IEEE) (2005)
  • H. Mrabet, Z. Marrakchi, H. Mehrez, A. Tissot : “Implementation of Scalable Embedded FPGA for SOC”, ReCoSoC 2005 - 1^st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France, pp. 74-77 (2005)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation”, ReConFig 2005 - International Conference on Reconfigurable Computing and FPGAs, Puebla City, Mexico, pp. 21-25, (IEEE Computer Society) (2005)
• 2004
  • H. Mrabet, Z. Marrakchi, H. Mehrez, A. Tissot : “Automatic Layout of Scalable Embedded Field Programmable Gate Array”, ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pp. 469-472, (IEEE) (2004)