科研组 : CIAN - Analog and Digital Integrated Circuit
Axes : ASN (👥👥), SSR (👥👥), AID (👥).
Roselyne Chotin Campus Pierre et Marie Curie 24-25/406
The research areas of CIAN team focus on design methods for analog and digital components which are integrated on the same chip (AMS-SOC). The main aim is to design generic components that can be adapted for a wide range of applications. Components differ depending upon the nature of the signal to process : signal processors (DSP), digital ASIC, programmable logic component (FPGA), analog circuits, multi-standard RF components and SOC Clocks. The CIAN team proposes a solution for design reuse.
The on-going research projects within the team are : CORIOLIS, ARITHLIB, CAIRO+ and HODISS.
AMS circuits, FPGA, ASIC, Full Custom, RF Interface, Circuit Reuse, Intellectual Property (AMS IP), Electronic Design Automation (EDA), Analog to Digital Converters (DAC and ADC, SOC Clocks.
- R. Iskander, M.‑M. Louërat, A. Kaiser : “Hierarchical sizing and biasing of analog firm intellectual properties”, Integration, the VLSI Journal, vol. 46 (2), pp. 172-188, (Elsevier) [Iskander 2013]
- A. Lévêque, F. Pêcheux, M.‑M. Louërat, H. Aboushady, F. Cenni, S. Scotti, A. Massouri, L. Clavier : “Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System”, Design, Automation and Test in Europe (DATE'12), Dresden, Germany, pp. 739-744, (EDAA Publishing) [Lévêque 2012]
- D. Galayko, Ph. Basset : “A General Analytical Tool for the Design of Vibration Energy Harvesters (VEHs) Based on the Mechanical Impedance Concept”, IEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications, vol. 58 (2), pp. 299-311, (Institute of Electrical and Electronics Engineers (IEEE)) [Galayko 2011a]
- Ah. Ashry, H. Aboushady : “Simple architecture for subsampling LC-based ΣΔ modulators”, Electronics Letters, vol. 46 (18), pp. 1263-1264, (IET) [Ashry 2010f]
- S. Belloeil, R. Chotin‑Avot, H. Mehrez : “Exploring redundant arithmetics in computer-aided design of arithmetic datapaths”, Integration, the VLSI Journal, vol. 46 (2), pp. 104-118, (Elsevier) [Belloeil 2013]
- U. Farooq, Z. Marrakchi, H. Mehrez : “Tree Based Heterogeneous FPGA Architectures, Application Specific Exploration and Optimization”, (Springer), (ISBN: 978-1-4614-3593-8) [Farooq 2012b]
- H. Parvez, H. Mehrez : “Application-Specific Mesh-based Heterogeneous FPGA Architectures”, vol. 202, (Springer), (ISBN: 978-1-4419-7927-8) [Parvez 2011a]
- F. Anceau, Y. Bonnassieux : “Conception de circuits VLSI. Du composant au système”, 315 pages, (Dunod), (ISBN: 978-2-10-050036-9) [Anceau 2007b]
- Ah. Ashry, H. Aboushady : “A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΣΔ ADC with a FoM of 1pJ/bit in 130nm CMOS”, CICC 2011 - Custom Integrated Circuits Conference, San Jose, CA, United States, pp. 1-4, (IEEE) [Ashry 2011a]
- J.‑M. Akre, J. Juillard, D. Galayko, E. Colinet : “Synchronization Analysis of Networks of Self-sampled All-Digital Phase-Locked Loops”, IEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications, vol. 59 (4), pp. 708-720, (Institute of Electrical and Electronics Engineers (IEEE)) [Akre 2012]