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Projects CIAN

Team : CIAN

    CORIOLIS - Platform for physical synthesis of integrated circuits

    Coriolis is an experimental integrated platform for the research, development and evaluation of new back-end VLSI design flows. Interconnect scaling to nanometer processes presents many difficult challenges to CAD flows. Currently academic research on back-end tend to address only specific algorithmic issues separately, although one key issue to address is the cooperation of multiple algorithmic tools. CORIOLIS, our platform, is based on an integrated C++ database around which all tools consistently interact and collaborate. This platform currently includes a timing-driven global place and route flow.

    Project leader : Jean-Paul CHAPUT
    More details here
  • CAIRO - Analog IP Design

    Our purpose is to provide a language for designing generators of analog functions, that can be easily ported to new set of specfications and new technologogy processes. We are currently developing such a language that is called CAIRO+ The CAIRO+ language supports the four steps of a design flow based on net-list and layout templates. This language is aimed to help the designer to capture his knowledge, thus creating a library of layout-aware analog functions. It is based on C++ language. The design flow relevant to CAIRO+ is the following : ->net-list and layout template capture, ->design space exploration (managing electrical constraints) ->shape function computation (managing geometrical constraints) ->layout generation (place and route) CAIRO+ allows creating complex hierarchical analog function generators by using existing generators of simpler functions. It is an answer to the problem of Analog and Mixed IPs. As a demonstration of the CAIRO+'s capabilities, we are developping Analog to Digital converters, specially Sigma Delta.

    Project leader : Marie-Minerve LOUËRAT
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