| Current teams : | ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL |
| Former team : | ACASA |
| Publications ALSOC | 2023 | 2024 | Total |
|---|---|---|---|
| Books | 0 | 0 | 0 |
| Edited books | 0 | 0 | 0 |
| Journal articles | 6 | 1 | 7 |
| Book chapters | 0 | 0 | 0 |
| Conference papers | 9 | 7 | 16 |
| Habilitations | 0 | 0 | 0 |
| Thesis | 3 | 2 | 5 |
- É. André, Th. Chatain, E. Encrenaz, L. Fribourg : “An Inverse Method for Parametric Timed Automata”, Proceedings of the Second Workshop on Reachability Problems in Computational Models (RP 2008), vol. 223, Electronic Notes in Theoretical Computer Science, Liverpool, United Kingdom, pp. 29-46, (Elsevier) [André 2008]
- O. Certner, P. Palatin, Zh. Li, O. Temam, F. Arzel, N. Drach : “A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs”, DATE Design Automation and Test in Europe Conference, Munich, Germany, pp. 740-745, (IEEE) [Certner 2008a]
- O. Certner, Zh. Li, P. Palatin, O. Temam, F. Arzel, N. Drach : “A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs”, MULTIPROG International Workshop on Programmability Issues for Multi-Core Computers, Göteberg, Sweden [Certner 2008b]
- E. Faure, D. Genius : “Telecommunication Application Modelling with Multi Writer Multi Reader Channels: a Case Study”, FDL Forum on Specification & Design Languages, Stuttgart, Germany, pp. 241-242, (IEEE) [Faure 2008]
- D. Genius, N. Pouillon, A. Greiner : “Design Space Explorer : Un Outil de Co-Conception pour Plate-formes Multi-processeurs sur Puce”, CNFM Coordination Nationale pour la Formation en Micro-nanoélectronique, St Malo, France, pp. 33-38 [Genius 2008]
- I. Miro Panades, F. Clermidy, P. VIVET, A. Greiner : “Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture”, NoC ACM/IEEE International Symposium on Networks-on-Chip, Newcastle, United Kingdom, pp. 139-148, (IEEE) [Miro Panades 2008]
- Zh. Zhang, A. Greiner : “Un Algorithme de Routage Reconfigurable pour la Tolérance aux Fautes dans le micro-réseau DSPIN”, Colloque national GDR SOC-SIP, Paris, France [Zhang 2008a]
- Zh. Zhang, A. Greiner, S. Taktak : “A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip”, The 45th annual Design Automation Conference (DAC), Anaheim, California, United States, pp. 441-446 [Zhang 2008b]