LIP6 2004/005
- أطروحة
Analyse temporelle des circuits intégrés digitaux CMOS, pour les technologies profondément submicroniques - G. Avot
- 219 pages - 25/02/2003- document en - http://www.lip6.fr/lip6/reports/2004/lip6.2004.005.pdf - 1,232 Ko
- للاتصال : Gregoire.Avot (at) nulllip6.fr
- Ancien Thème : ASIM
- كـلمـات مـفـتاح : Timing analysis, Stability analysis, Coupling capacitance, Interconnect resistance, Switching noise.
- Publisher : Francois.Dromard (at) nulllip6.fr
In timing analysis of deep-submicronic digital CMOS circuits, interconnect resistances and coupling capacitances become more and more significant. We present delay effect due to these elements, and we deduce that the gate's load can be modelled as a PI cells. Furthermore interconnect delays can be computed with Elmore delay. Coupling capacitances effects on delays are taken into account with Miller effect, and influence of noise switching. So, we present how to introduce these models in Hitas, the existing timing analyser made in our laboratory. To use these models, we also present a set of algorithm based on stability analysis, and some enhancements to get results not too pessimistic. Then, we present a software that include all theses features.