Publications 2004-2024

• 2024
  • D. Genius, L. Apvrille : “Cycle-Accurate Virtual Prototyping with Multiplicity”, Proceedings of the 12^th International Conference on Model-Based Software and Systems Engineering - MODELSWARD, vol. 1, Rome, Italy, pp. 187-194, (SCITEPRESS - Science and Technology Publications), (ISBN: 978-989-758-682-8) (2024)
• 2023
  • D. Genius, L. Apvrille : “A Tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML Models”, DVCon 2023 (research track), Munich (Germany), Germany, pp. 1-6, (Accellera) (2023)
  • D. Genius, L. Apvrille : “Hierarchical Design of Cyber-Physical Systems”, 11^th International Conference on Model-Based Software and Systems Engineering - MODELSWARD, Lisbon (virtual ), Portugal, pp. 117-124, (SciTePress) (2023)
• 2022
  • D. Genius, R. Chotin : “Model to Hardware : System-Level Modeling for Wearable Devices”, ModelsWARD, Virtual Conference, France (2022)
• 2021
  • D. Genius, I. Bournias, L. Apvrille, R. Chotin : “Model-Based Virtual Prototyping of CPS: Application to Bio-Medical Devices”, International Conference on Model-Driven Engineering and Software Development, vol. 1361, CCIS, Valletta, Malta, pp. 74-96, (Springer, Cham) (2021)
  • R. Cortés Porto, D. Genius, L. Apvrille : “Handling causality and schedulability when designing and prototyping cyber-physical systems”, Software and Systems Modeling, vol. 20 (1), (Springer Verlag) (2021)
• 2020
  • F. Pêcheux, L. Andrade Porras, M.‑M. Louërat, I. Bournias, R. Chotin, D. Genius : “Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions”, 2020 Forum for Specification and Design Languages (FDL), Kiel, Germany, pp. 1-8, (IEEE) (2020)
  • D. Genius, I. Bournias, L. Apvrille, R. Chotin : “High-level Partitioning and Design Space Exploration for Cyber Physical Systems”, Proceedings of the 8^th International Conference on Model-Driven Engineering and Software Development - Volume 1: MODELSWARD, Valletta, Malta, pp. 84-91, (SCITEPRESS) (2020)
  • D. Genius, L. Apvrille : “Hardware / Software / Analog System Partitioning with SysML and SystemC-AMS”, 10^th European Congress on Embedded Real Time Systems, Toulouse, France (2020)
  • D. Genius, R. Cortés Porto, L. Apvrille, F. Pêcheux : “A Framework for Multi-level Modeling of Analog/Mixed Signal Embedded Systems”, Model-Driven Engineering and Software Development, vol. 1161, Communications in Computer and Information Science, Prague, Czechia, pp. 201-224, (Springer) (2020)
• 2019
  • D. Genius : “Scalability of TTool’s AMS extensions: a case study”, International Workshop on Reconfigurable and Communication-centric Cyber-Physical Systems (ReCoCyPS 2019), York, United Kingdom (2019)
  • D. Genius, L. Apvrille, L. Li : “High-level modeling of communication-centric applications: Extensions to a system-level design and virtual prototyping tool”, Microprocessors and Microsystems: Embedded Hardware Design, (Elsevier) (2019)
  • D. Genius, R. Cortés Porto, L. Apvrille, F. Pêcheux : “A Tool for High-Level Modeling of Analog/Mixed Signal Embedded Systems”, Proceedings of the 7^th International Conference on Model-Driven Engineering and Software Development, Prague, Czechia, pp. 435-442, (Scitepress) (2019)
  • R. Cortés Porto, D. Genius, L. Apvrille : “Modeling and Virtual Prototyping for Embedded Systems on Mixed-Signal Multicores”, RAPIDO '19 Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, Valencia, Spain (2019)
• 2018
  • Letitia W. Li, D. Genius, L. Apvrille : “Formal and Virtual Multi-level Design Space Exploration.”, chapter in International Conference on Model-Driven Engineering and Software Development., pp. 47-71, (Springer) (2018)
  • D. Genius, M.‑M. Louërat, F. Pêcheux, L. Apvrille, Haralampos‑G. Stratigopoulos : “Modeling Heterogeneous Embedded Systems with TTool”, DUHDe 2018 — 5^th Workshop on Design Automation for Understanding Hardware Designs, Dresden, Germany (2018)
  • D. Genius, Letitia W. Li, L. Apvrille, T. Tanzi : “Multi-level Latency Evaluation with an MDE Approach”, Proceedings of the 6^th International Conference on Model-Driven Engineering and Software Development, Funchal, Portugal (2018)
  • D. Genius, L. Apvrille : “System-Level Design and Virtual Prototyping of a Telecommunication Application on a NUMA Platform”, 2018 13^th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, France, (IEEE) (2018)
• 2017
  • D. Genius, L. Apvrille : “System-Level Design for Communication-Centric Task Farm Applications”, 12^th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, Madrid, Spain (2017)
  • D. Genius, L. Li, L. Apvrille : “Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design”, Modeling Languages, Tools and Architectures, Methodologies, Processes and Platforms, Applications and Software Development (MODELSWARD), Porto, Portugal (2017)
• 2016
  • D. Genius, L. Apvrille : “Virtual Yet Precise Prototyping: An Automotive Case Study”, Proceedings of the 8^th European Congress on Embedded Real Time Software and Systems (ERTS 2016), TOULOUSE, France, pp. 691-700 (2016)
  • L. Li, L. Apvrille, D. Genius : “Virtual Prototyping of Automotive Systems: Towards Multi-level Design Space Exploration”, Conference on Design and Architectures for Signal and Image Processing, Rennes, France (2016)
• 2014
  • Th. Carle, M. Djemal, D. Genius, F. Pêcheux, D. Potop‑Butucaru, R. De Simone, F. Wajsbürt, Zh. Zhang : “Reconciling performance and predictability on a many-core through off-line mapping”, Proceedings ReCoSoC 2014, Montpellier, France, pp. 1-8, (IEEE) (2014)
• 2013
  • D. Genius, A. Munier‑Kordon, Kh. Zine el Abidine : “Space Optimal Solution for Data Reordering in Streaming Applications on NoC based MPSoC”, Journal of Systems Architecture, vol. 59 (7), pp. 455-467, (Elsevier) (2013)
  • D. Genius : “Measuring Memory Latency for Software Objects in a NUMA System-on-Chip Architecture”, 8^th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, Darmstadt, Germany, pp. 1-8, (IEEE) (2013)
• 2012
  • D. Genius, Kh. Zine el Abidine : “Handling Out-of-order Arrival for Parallel Streaming Applications on Clustered MPSoC”, Conference on Design of Circuits and Integrated Systems, Avignon, France (2012)
  • D. Genius, Kh. Zine el Abidine : “A Hierarchical Approach to the Out-of-order Arrival of Frames in Video Streaming Applications on Clustered MPSoC”, International Conference on Design and Architecture for Signal and Image Processing, Karlsruhe, Germany, pp. 1-8, (IEEE) (2012)
  • D. Genius, Kh. Zine el Abidine : “A Solution to the Data Re-ordering Problem for Multi-Pipeline Streaming Applications on Clustered MPSoC”, 7^th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, United Kingdom, pp. 1-8, (IEEE) (2012)
• 2011
  • D. Genius, N. Pouillon : “Analyzing Software Inter-Task Communication Channels on a Clustered Shared Memory Multi Processor +System-on-Chip”, International Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, pp. 1-8, (IEEE) (2011)
  • D. Genius, N. Pouillon : “Monitoring Software Communication Channels on a Shared Memory Multi-Processor System on Chip”, ReCoSoC Reconfigurable Communication-centric SoCs, Montpellier, France, pp. 1-8, (IEEE) (2011)
  • D. Genius, E. Faure, N. Pouillon : “Mapping a Telecommunication Application on a Multiprocessor System-on-Chip”, chapter in Algorithm-Architecture Matching for Signal and Image Processing, vol. 73, Lecture Notes in Electrical Engineering, pp. 53-77, (Springer LNEE), (ISBN: 978-90-481-9964-8) (2011)
• 2009
  • A. Greiner, E. Faure, N. Pouillon, D. Genius : “A Generic Hardware / Software Communication Middleware for Streaming Applications on Shared Memory Multi Processor Systems-on-Chip”, FDL Forum on Specification & Design Languages, Nice, France, pp. 1-4 (2009)
  • D. Genius, A. Munier‑Kordon, Kh. Zine el Abidine : “A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor”, Euro-Par European Conference on Parallel computing, vol. 5704, Lecture Notes in Computer Science, Delft, Netherlands, pp. 216-227, (Springer) (2009)
• 2008
  • D. Genius, N. Pouillon, A. Greiner : “Design Space Explorer : Un Outil de Co-Conception pour Plate-formes Multi-processeurs sur Puce”, CNFM Coordination Nationale pour la Formation en Micro-nanoélectronique, St Malo, France, pp. 33-38 (2008)
  • E. Faure, D. Genius : “Telecommunication Application Modelling with Multi Writer Multi Reader Channels: a Case Study”, FDL Forum on Specification & Design Languages, Stuttgart, Germany, pp. 241-242, (IEEE) (2008)
• 2007
  • D. Genius, E. Faure, N. Pouillon : “Deploying a Telecommunication on Multiprocessor Systems-on-Chip”, International Conference on Design and Architectures for Signal and Image Processing, Grenoble, France, pp. 1-8 (2007)
• 2006
  • E. Faure, A. Greiner, D. Genius : “A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications”, ReCoSoC Reconfigurable Communication-centric SoCs, Montpellier, France, pp. 237-242 (2006)
• 2004
  • S. Berrayana, E. Faure, D. Genius, F. Pétrot : “Modular on chip multi processor for routing applications”, Euro-Par 2004 - 10^th European Conference on Parallel computing, vol. 3149, Lecture Notes in Computer Science, Pise, Italy, pp. 847-855, (Springer) (2004)