BAZARGAN SABET Pirouz
Maître de Conférences
Équipe : CIAN
Tel: 01 44 27 71 18, Pirouz.Bazargan-Sabet (at) nulllip6.fr
https://lip6.fr/Pirouz.Bazargan-Sabet
Équipe : CIAN
- Sorbonne Université - LIP6
Boîte courrier 169
Couloir 24-25, Étage 5, Bureau 502
4 place Jussieu
75252 PARIS CEDEX 05
Tel: 01 44 27 71 18, Pirouz.Bazargan-Sabet (at) nulllip6.fr
https://lip6.fr/Pirouz.Bazargan-Sabet
Publications 1997-2018
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2018
- E. Guthmuller, C. Fuguet, P. Vivet, C. Bernard, I. Miro‑Panades, J. Durupt, E. Beigne, D. Lattard, S. Cheramy, A. Greiner, Quentin L. Meunier, P. Bazargan Sabet : “A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches”, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Dresden, Germany, pp. 318-321, (IEEE) (2018)
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2016
- B. Robisson, M. Agoyan, P. Soquet, S. Le‑Henaff, F. Wajsbürt, P. Bazargan‑Sabet, G. Phan : “Smart security management in secure devices”, Journal of Cryptographic Engineering, (Springer) (2016)
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2015
- B. Robisson, M. Agoyan, P. Soquet, S. Le Henaff, F. Wajsbürt, P. Bazargan‑Sabet, G. Phan : “SMART SECURITY MANAGEMENT IN SECURE DEVICES”, PROOFS: Security Proofs for Embedded Systems, Saint-Malo, France (2015)
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2014
- B. Ouattara, L. Doyen, D. Ney, H. Mehrez, P. Bazargan‑Sabet : “Power grid redundant path contribution in system on chip (SoC) robustness against electromigration”, Microelectronics Reliability, vol. 54 (9-10), pp. 1702-1706, (Elsevier) (2014)
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2013
- D. Fujimoto, N. Miura, M. Nagata, Y. Hayashi, N. Homma, Y. Hori, T. Katashita, K. Sakiyama, Th. Le, J. Bringer, P. Bazargan Sabet, J.‑L. Danger : “On-Chip Power Noise Measurements of Cryptographic VLSI Circuits and Interpretation for Side-Channel Analysis”, International Symposium on Electromagnetic Compatibility (EMC Europe), Brugge, Belgium, pp. 405-410, (IEEE) (2013)
- B. Ouattara, L. Doyen, D. Ney, H. Mehrez, P. Bazargan‑Sabet, F. Bana : “Redundancy Method to assess Electromigration Lifetime in power grid design”, IEEE International Interconnect Technology Conference (IITC),, Kyoto, Japan, pp. 81-83, (IEEE) (2013)
- P. Bazargan Sabet, D. Le Dû : “Identifying Signal Correlations Using Discrete Event Simulation”, IEEE International New Circuits and Systems Conference, Paris, France, pp. 349-352 (2013)
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2011
- B. Robisson, M. Agoyan, S. Bouquet, M. Nguyen, S. Le Henaff, P. Soquet, G. Phan, F. Wajsbürt, P. Bazargan‑Sabet, N. Drach : “Management of the security in smart secure devices”, SSI 2010 - Smart Systems Integration, Dresden, Germany, pp. 1-9 (2011)
- B. Robisson, M. Agoyan, S. Le Henaff, P. Soquet, G. Phan, F. Wajsbürt, P. Bazargan‑Sabet : “Implementation of complex strategies of security in secure embedded systems”, NTMS 2011 - 4th IFIP International Conference on New Technologies, Mobility and Security, Paris, France, pp. 1-5, (IEEE) (2011)
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2010
- M. Agoyan, P. Bazargan Sabet, K. Bekkou, B. Sylvain, S. Le Henaff, E. Lepavec, M. Nguyen, G. Phan, B. Robisson, P. Soquet, F. Wajsbürt : “Smart On Smart”, Colloque « Systèmes embarqués, sécurité et sûreté de fonctionnement », Toulouse, France (2010)
- B. Darvish, P. Bazargan Sabet, P. Renault : “A methodology for Analysis of Voltage Drop in VLSI Digital Circuits”, International Conference on Modeling, Simulation and Control (ICMSC'2010), Cairo, Egypt (2010)
- A. Bara, P. Bazargan Sabet, R. Chevallier, E. Encrenaz, D. Le Dû, P. Renault : “Formal Verification of Timed VHDL Programs”, Forum on Specification & Design Languages, FDL 2010, Southampton, United Kingdom, pp. 80-85, (IET) (2010)
- M. Agoyan, B. Robisson, M. Nguyen, P. Bazargan‑Sabet, G. Phan, S. Le Henaff : “SOS An innovative secure system architecture”, Cryptarchi, Paris, France (2010)
- P. Soquet, B. Robisson, M. Agoyan, G. Phan, P. Bazargan Sabet, F. Wajsbürt : “Strategy Of Security on Smart On Smart”, PACA Security Trends In embedded Security, Gardanne, France (2010)
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2008
- P. Renault, P. Bazargan Sabet : “A Novel Method to Determine the RC Interconnect Circuit Outputs”, DCIS International Conference on Design of Circuits and Integrated Systems, Grenoble, France (2008)
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2006
- N. Abdallah, P. Bazargan Sabet : “Modeling the Effects of Input Slew Rate and Temporal Proximity of Input Transitions in Event-Driven Simulation”, SSST IEEE Southeastern Symposium on System Theory, Cookeville, Tenessess, United States, pp. 185-189, (IEEE) (2006)
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2005
- P. Renault, P. Bazargan Sabet : “Capturing RC-Interconnect Effect in Crosstalk Analysis”, MIXDES 2005 - 12th International conference on Mixed Design of Integrated Circuits and Systems, Krakow, Poland, pp. 309-314 (2005)
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2004
- P. Renault, P. Bazargan Sabet : “Splitting of RC-Network for Accurate Model Reduction”, ICM 2004 - 16th International Conference on Microelectronics, Tunis, Tunisia, pp. 734-737, (IEEE) (2004)
- P. Renault, P. Bazargan Sabet : “Determining The Analytic Waveform of an RC-Circuit Output”, MIXDES Mixed Design of Integrated Circuits and Systems, Szczecin, Poland, pp. 363-368 (2004)
- P. Renault, P. Bazargan Sabet : “A Simplified Circuit to Model RC Interconnect”, WSEAS Transactions on circuits and systems, vol. 3 (3), pp. 431-436, (World Scientific and Engineering Academy and Society (WSEAS)) (2004)
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2003
- P. Bazargan Sabet, P. Renault : “An Event-Driven Approach to Crosstalk Noise Analysis”, 36th Annual Simulation Symposium (ANSS'36), Orlando, FL, United States, pp. 319-326, (IEEE) (2003)
- P. Bazargan Sabet, P. Renault : “Using Symbolic Simulation to Exhibit Worst Case Crosstalk”, 4th IEEE Latin-American Test Workshop (LATW'03), Natal, Brazil, pp. 264-268 (2003)
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2002
- D. Le Dû, P. Renault, P. Bazargan Sabet : “A MOS Transistor Model for Peak Voltage Calculation of Crosstalk Noise”, 9th International Conference on Electronics, Circuits and Systems, Dubrovnick, Croatia, pp. 773-776, (IEEE) (2002)
- P. Renault, D. Le Dû, F. Ilponse, P. Bazargan Sabet : “Conception d’un outil d’évaluation des bruits diaphoniques dans les circuits submicroniques”, Vèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2002), Grenoble, France (2002)
- P. Renault, P. Bazargan Sabet : “Modèle du transistor MOS à canal court en vue de l’évaluation du bruit de diaphonie dans les circuits submicroniques”, Troisième colloque du GDR CAO de circuits et systèmes intégrés, Paris, France, pp. 125-128 (2002)
- D. Le Dû, P. Bazargan Sabet : “Structuration des données dans les outils de vérification back-end”, Troisième colloque du GDR CAO de circuits et systèmes intégrés, Paris, France, pp. 129-132 (2002)
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2001
- M.‑M. Paget, P. Bazargan Sabet, A. Greiner : “An Example of Practice Based Engineering Education : the Design of a Microprogrammed MIPS Processor with the Alliance CAD System”, Computer Aided Learning In Engineering (CALIE'2001), Tunis, Tunisia, pp. 47-50 (2001)
- P. Bazargan Sabet, L. Vuillemin : “An Approach to Mapping the Timing Behavior of VLSI Circuits on Emulators”, 12th IEEE International Workshop on Rapid System Prototyping, Monterey, California, United States, pp. 168-173, (IEEE) (2001)
- P. Renault, F. Ilponse, P. Bazargan Sabet : “Modèle d’évaluation du bruit de diaphonie pour les technologies submicroniques”, IVèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2001), Strasbourg, France, pp. 188-189 (2001)
- P. Bazargan Sabet, F. Ilponse : “A Model for Crosstalk Evaluation in Deep Submicron Processes”, International Symposium on Quality Electronic Design (ISQED'2001), San Jose, California, United States, pp. 139-144, (IEEE) (2001)
- P. Bazargan Sabet, F. Ilponse : “Modeling Croostalk Noise for Deep Submicron Verification Tools”, Design Automation and Test in Europe Conference (DATE'2001), Munich, Germany, pp. 530-534, (IEEE) (2001)
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2000
- L. Vuillemin, P. Bazargan Sabet : “Timed simulation of VLSI circuits using a FPGA net”, Applied Informatics (IASTED AI 2000), Innsbruck, Austria (2000)
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1999
- F. Ilponse, P. Bazargan Sabet : “CRISE : Un Outil d’Evaluation des Risques dus à la Diaphonie dans les Circuits Intégrés fortement Sub-Microniques”, Colloque CAO de Circuits Intégrés et Systèmes GDR 732, Aix-en-Provence, France (1999)
- L. Vuillemin, P. Bazargan Sabet : “Simulation logico temporelle de circuits VLSI à l’aide d’un réseau de FPGA”, Colloque CAO de Circuits Intégrés et Systèmes GDR 732, Aix-en-Provence, France (1999)
- F. Dromard, Y. Body, M.‑M. Paget, A. Greiner, P. Bazargan Sabet, F. Pétrot : “Interactive Learning of Processor Architecture”, 5th International Conference on Computer Aided Engineering Education (CAEE'99), Sofia, Bulgaria, pp. 123-129 (1999)
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1998
- A. Lester, P. Bazargan Sabet, A. Greiner : “YAGLE, a Second generation Functional Abstractor for CMOS VLSI Circuits”, 10th International Conference on Microelectronics (ICM'98), Monastir, Tunisia, pp. 265-268, (IEEE) (1998)
- A. Lester, P. Bazargan Sabet, A. Greiner : “Circuit Disassembly for Verification and functional Abstraction of CMOS Circuits”, Sophia Antipolis forum on MicroElectronics (SAME'98), Sophia Antipolis, France, pp. 60-63 (1998)
- A. Guettaf, P. Bazargan Sabet : “Using Node Replication to Improve Circuit’s Partition in Distributed Logic Simulation”, 12th European Simulation Multiconference, Manchester, United Kingdom, pp. 235-237 (1998)
- A. Guettaf, P. Bazargan Sabet : “Efficient Partitioning Method for Distributed Logic Simulation of VLSI Circuits”, 31st Annual Simulation Symposium, Boston, MA, United States, pp. 196-201, (IEEE) (1998)
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1997
- N. Abdallah, P. Bazargan Sabet, J. Dunoyer : “SWISSE: A Fast Switch-Level Timing Simulator with Slope Effects for Large Digital MOS Circuits”, 4th IEEE International Conference on Electronics Circuits and Systems (ICECS'97), Cairo, Egypt, pp. 875-879 (1997)
- J. Dunoyer, N. Abdallah, P. Bazargan Sabet : “Méthodes Probabilistes et Problèmes de Corrélations pour l’Evaluation de la Consommation des Circuits VLSI”, Journées Faible Tension Faible Consommation, Paris, France, pp. 131-134 (1997)
- J. Dunoyer, L. Vuillemin, P. Bazargan Sabet : “Méthodes Probabilistes pour l’Evaluation de la Consommation des Circuits Intégrés VLSI”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 116-119 (1997)
- N. Abdallah, P. Bazargan Sabet : “Technique de Simulation Event-Driven en Vue d’une Simulation Mixte Efficace”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 22-25 (1997)
- A. Lester, A. Greiner, P. Bazargan Sabet : “Un Outil d’Evaluation de la Consommation Basée sur l’Extraction d’un Réseau de Portes Caractérisées”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 128-131 (1997)