GREINER Alain
Professore Emerito
Gruppo di ricerca : ALSOC
Data di partenza : 08/31/2022
https://lip6.fr/Alain.Greiner
Gruppo di ricerca : ALSOC
Data di partenza : 08/31/2022
https://lip6.fr/Alain.Greiner
Pubblicazioni 1997-2021
-
2021
- P. VIVET, E. Guthmuller, Y. Thonnart, G. Pillonnet, C. Fuguet, I. Miro‑Panades, G. Moritz, J. Durupt, Ch. Bernard, D. Varreau, J. Pontes, S. Thuries, D. Coriat, M. Harrand, D. Dutoit, D. Lattard, L. Arnaud, J. Charbonnier, P. Coudrain, A. Garnier, F. Berger, A. Gueugnot, A. Greiner, Q. Meunier, A. Farcy, A. Arriordaz, S. ChĂ©ramy, F. Clermidy : “IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management”, IEEE Journal of Solid-State Circuits, vol. 56 (1), pp. 79-97, (Institute of Electrical and Electronics Engineers) (2021)
-
2020
- P. VIVET, E. Guthmuller, Y. Thonnart, G. Pillonnet, G. Moritz, I. Miro‑Panades, C. Fuguet, J. Durupt, Ch. Bernard, D. Varreau, J. Pontes, S. Thuries, D. Coriat, M. Harrand, D. Dutoit, D. Lattard, L. Arnaud, J. Charbonnier, P. Coudrain, A. Garnier, F. Berger, A. Gueugnot, A. Greiner, Quentin L. Meunier, A. Farcy, A. Arriordaz, S. ChĂ©ramy, F. Clermidy : “A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters”, 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, United States, pp. 46-48, (IEEE) (2020)
-
2018
- E. Guthmuller, C. Fuguet, P. Vivet, C. Bernard, I. Miro‑Panades, J. Durupt, E. Beigne, D. Lattard, S. Cheramy, A. Greiner, Quentin L. Meunier, P. Bazargan Sabet : “A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches”, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Dresden, Germany, pp. 318-321, (IEEE) (2018)
-
2017
- H. Liu, Quentin L. Meunier, A. Greiner : “Decoupling Translation Lookaside Buffer Coherence from Cache Coherence”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Bochum, Germany, pp. 92-97, (IEEE) (2017)
-
2016
- M. Karaoui, P.‑Y. PĂ©neau, Quentin L. Meunier, F. WajsbĂĽrt, A. Greiner : “Exploiting Large Memory using 32-bit Energy-Efficient Manycore Architectures”, 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Lyon, France, pp. 61-68, (IEEE) (2016)
-
2015
- H. Liu, C. DĂ©vigne, L. Garcia, Quentin L. Meunier, F. WajsbĂĽrt, A. Greiner : “RWT: Suppressing Write-Through Cost When Coherence is Not Needed”, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, pp. 434-439, (IEEE) (2015)
- M. Karaoui, Quentin L. Meunier, F. WajsbĂĽrt, A. Greiner : “GECOS : MĂ©canisme de synchronisation passant Ă l’échelle Ă plusieurs lecteurs et un Ă©crivain pour structures chaĂ®nĂ©es”, Revue des Sciences et Technologies de l'Information - SĂ©rie TSI : Technique et Science Informatiques, vol. 34, pp. 53-78, (Lavoisier) (2015)
-
2014
- C. Fuguet, A. Greiner : “Fault-Tolerance Mechanisms for Permanent Failures in a Coherent Shared-Memory Many-Core Architecture”, Colloque GDR SoC-SiP, Paris, France (2014)
- Zh. Zhang, D. Refauvelet, A. Greiner, M. Benabdenbi, F. PĂŞcheux : “On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22 (6), pp. 1364-1376, (IEEE) (2014)
- M. Karaoui, Quentin L. Meunier, F. WajsbĂĽrt, A. Greiner : “MĂ©canisme de synchronisation scalable Ă plusieurs lecteurs et un Ă©crivain”, ConfĂ©rence en ParallĂ©lisme, Architecture et Systèmes, ComPAS 2014, Neuchâtel, Switzerland (2014)
-
2012
- E. Guthmuller, I. Miro‑Panades, A. Greiner : “Adaptive Stackable 3D Cache Architecture for Manycores”, VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on, Amherst, MA, United States, pp. 39-44 (2012)
-
2011
- Zh. Zhang, D. Refauvelet, A. Greiner, M. Benabdenbi, F. PĂŞcheux : “Localization of Damaged Resources in NoC Based Shared-Memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure”, The 29th IEEE VLSI Test Symposium (VTS), Dana Point, California, United States (2011)
- J. Porquet, A. Greiner, Ch. Schwarz : “NoC-MPU: A Secure Architecture for Flexible Co-Hosting on Shared Memory MPSoCs”, DATE Design Automation and Test in Europe Conference Grenoble, France, March 2011, Grenoble, France, pp. 591-594, (IEEE) (2011)
- I. MaĂŻa Pessoa, A. Vieira De Mello, A. Greiner, F. PĂŞcheux : “Parallel TLM simulation of MPSoC on SMP workstations: Influence of communication locality”, ICM 2010 - 22nd International Conference on Microelectronics, Cairo, Egypt, pp. 359-362 (2011)
-
2010
- F. PĂŞcheux, Kh. Zine el Abidine, A. Greiner : “Early power estimation in heterogeneous designs using Soclib and Systemc-ams”, International Workshop on Power And Timing Modeling Optimization and Simulation, PATMOS, vol. 6448, Lecture Notes in Computer Science, Grenoble, France, pp. 252, (Springer) (2010)
- Zh. Zhang, A. Greiner, M. Benabdenbi : “Fully Distributed Initialization Procedure for a 2D-Mesh NoC, Including Off Line BIST and Partial Deactivation of Faulty Components”, The 16th IEEE International On-Line Testing Symposium (IOLTS), Corfu, Greece, pp. 194-196 (2010)
- A. Vieira De Mello, I. MaĂŻa Pessoa, A. Greiner, F. PĂŞcheux : “Parallel Simulation of SystemC TLM 2.0 Compliant MPSoC on SMP Workstations”, DATE 2010 - Design, Automation & Test in Europe Conference & Exhibition, Dresden, Germany, pp. 606-609 (2010)
-
2009
- J. Porquet, Ch. Schwarz, A. Greiner : “Multi-compartment: A new architecture for secure co-hosting on SoC”, SoC International Symposium on System-on-Chip, Tampere, Finland, pp. 124-127, (IEEE) (2009)
- A. Greiner, E. Faure, N. Pouillon, D. Genius : “A Generic Hardware / Software Communication Middleware for Streaming Applications on Shared Memory Multi Processor Systems-on-Chip”, FDL Forum on Specification & Design Languages, Nice, France, pp. 1-4 (2009)
- N. Pouillon, A. BĂ©coulet, A. Vieira De Mello, F. PĂŞcheux, A. Greiner : “A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs”, IEEE/IFIP International Symposium on Rapid System Prototyping, 2009. RSP '09., Paris, France, pp. 116-122 (2009)
-
2008
- D. Genius, N. Pouillon, A. Greiner : “Design Space Explorer : Un Outil de Co-Conception pour Plate-formes Multi-processeurs sur Puce”, CNFM Coordination Nationale pour la Formation en Micro-nanoĂ©lectronique, St Malo, France, pp. 33-38 (2008)
- Zh. Zhang, A. Greiner, S. Taktak : “A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip”, The 45th annual Design Automation Conference (DAC), Anaheim, California, United States, pp. 441-446 (2008)
- I. Miro Panades, F. Clermidy, P. VIVET, A. Greiner : “Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture”, NoC ACM/IEEE International Symposium on Networks-on-Chip, Newcastle, United Kingdom, pp. 139-148, (IEEE) (2008)
- A. Sheibanyrad, A. Greiner : “Two Efficient Synchronous ⇔ Asynchronous Converters well-suited for Networks-on-Chip in GALS Architectures”, Integration, the VLSI Journal, vol. 41 (1), pp. 17-26, (Elsevier) (2008)
- Zh. Zhang, A. Greiner : “Un Algorithme de Routage Reconfigurable pour la TolĂ©rance aux Fautes dans le micro-rĂ©seau DSPIN”, Colloque national GDR SOC-SIP, Paris, France (2008)
- A. Sheibanyrad, A. Greiner, I. Miro‑Panades : “Multisynchronous and Fully Asynchronous NoCs for GALS Architectures”, IEEE Design & Test, vol. 25 (6), pp. 572-580, (IEEE) (2008)
-
2007
- R. Buchmann, A. Greiner : “A Fully Static Scheduling Approach for Fast Cycle Accurate SystemC Simulation of MPSoCs”, ICM International Conference on Microelectronics, Cairo, Egypt, pp. 105-108, (IEEE) (2007)
- A. Sheibanyrad, A. Greiner : “Hybrid-Timing FIFOs to use on Networks-on-Chip in GALS Architectures”, ESA International Conference on Embedded Systems and Applications, Las Vegas, Nevada, United States, pp. 27-33, (CSREA Press) (2007)
- I. Miro‑Panades, A. Greiner : “Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures”, NoC ACM/IEEE International Symposium on Networks-on-Chip, Princeton, NJ, United States, pp. 83-94, (IEEE), (ISBN: 0-7695-2773-6) (2007)
- M. Tuna, M. Benabdenbi, A. Greiner : “At-Speed Testing of Core-Based System-On-Chip Using an Embedded Micro-Tester”, VTS IEEE VLSI Test Symposium, Berkeley, California, United States, pp. 447-454, (IEEE) (2007)
- A. Sheibanyrad, I. Miro Panades, A. Greiner : “Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture”, DATE Design Automation and Test in Europe Conference 2007, Nice, France, pp. 1090-1095, (IEEE) (2007)
-
2006
- D. Galayko, R. Iskander, M.‑M. LouĂ«rat, A. Greiner : “RĂ©utilisation et migration d’amplificateurs avec CAIRO+”, JP CNFM JournĂ©es pĂ©dagogiques du CNFM, Saint Malo, France, pp. 35-39 (2006)
- I. Miro Panades, A. Greiner, A. Sheibanyrad : “A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach”, NanoNet International Conference on Nano-Networks, Lausanne, Switzerland, pp. 1-5, (IEEE) (2006)
- A. Sheibanyrad, A. Greiner : “Two Efficient Synchronous ⇔ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures”, International Workshop on Power And Timing Modeling Optimization and Simulation, vol. 4148, Lecture Notes in Computer Science, Montpellier, France, pp. 192-202, (Springer) (2006)
- A. Greiner, F. PĂ©trot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation”, 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'06), Montpellier, France, pp. 24-30, (UniversitĂ© Montpellier II) (2006)
- E. Faure, A. Greiner, D. Genius : “A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications”, ReCoSoC Reconfigurable Communication-centric SoCs, Montpellier, France, pp. 237-242 (2006)
- M. Tuna, M. Benabdenbi, A. Greiner : “T-Proc: An Embedded IEEE1500-Wrapped Cores Tester”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, pp. 493-496, (IEEE) (2006)
- M. Carrier, A. Greiner : “DĂ©tection d’obstacles en contexte routier par stĂ©rĂ©o vision sur un système intĂ©grĂ© sur puce”, JNRDM JournĂ©es Nationales du RĂ©seau Doctoral en MicroĂ©lectronique, Rennes, France, pp. 243-245 (2006)
- I. Miro Panades, A. Greiner, A. Sheibanyrad : “Micro-rĂ©seau sur puce compatible avec l’approche GALS”, JournĂ©es Nationales du RĂ©seau Doctoral de Micro-Ă©lectronique, Rennes, France, pp. 1-5 (2006)
- M. Tuna, M. Benabdenbi, A. Greiner : “STESOC: A Software-Based Test-Access-Mechanism Controller”, ETS IEEE European Test Symposium, Southampton, United Kingdom, pp. 91-96 (2006)
- E. Viaud, F. PĂŞcheux, A. Greiner : “An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles”, DATE Design Automation and Test in Europe Conference, Munich, Germany, pp. 94-99, (IEEE) (2006)
- R. Iskander, P. Nguyen‑Tuong, L. De Lamarre, V. Bourguet, M.‑M. LouĂ«rat, A. Greiner : “Automated Hierarchical Knowledge-Based Synthesis for Analog Cells using CAIRO+”, Design Automation and Test in Europe Conference (DATE'2006), Munich, Germany (2006)
- R. Buchmann, A. Greiner : “Automatic Translation of SystemC Simulation Model From VHDL RTL Model : a Semantic Approach”, DATE Design Automation and Test in Europe Conference, Munich, Germany (2006)
- F. PĂ©trot, A. Greiner, P. Gomez : “On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures”, 9th EUROMICRO Conference on Digital System Design (DSD'06), Dubrovnik, Croatia, pp. 53-60, (IEEE Computer Society) (2006)
- A. Greiner, F. PĂ©trot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip”, IV 2006 - IEEE Intelligent Vehicles Symposium, Tokyo, Japan, pp. 370-376, (IEEE) (2006)
-
2005
- M. Tuna, M. Benabdenbi, A. Greiner : “STESI: a new software-based strategy for testing socs containing wrapped IP cores”, MIXDES 2005 - 12th International conference on Mixed Design of Integrated Circuits and Systems, Krakow, Poland, pp. 459-464 (2005)
- M. Tuna, M. Benabdenbi, A. Greiner : “STESI: Testing wrapped IP cores using a dedicated Test Processor”, I-IP IEEE International Workshop on Infrastructure IP, Palm Springs, California, United States, pp. 60-66 (2005)
- R. Buchmann, A. Greiner : “Fast Functional SystemC Simulator using Static Scheduling”, DATE 2005 - Design Automation and Test in Europe Conference, MĂĽnchen, Germany (2005)
-
2004
- P. Nguyen‑Tuong, M.‑M. Rosset‑LouĂ«rat, A. Greiner : “Guidelines for Designing Smart and Reusable Analog IP Cores”, Sophia Antipolis MicroElectronics Forum (SAME), Sophia Antipolis, France, pp. 1-6 (2004)
- P. Nguyen‑Tuong, V. Bourguet, L. De Lamarre, M.‑M. Rosset‑LouĂ«rat, A. Greiner : “A Language to Design Generators of Analog Functions”, FDL 2004 - Forum on Specification & Design Languages, Lille, France, pp. 30-31 (2004)
- R. Buchmann, A. Greiner, F. PĂ©trot : “Fast Cycle Accurate Simulation To Simulate Event-Driven Behavior”, ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pp. 37-40, (IEEE) (2004)
- P. Nguyen‑Tuong, M.‑M. Rosset‑LouĂ«rat, A. Greiner : “Managing the Shape Function of Analog Devices in a Slicing Tree Floorplan”, Mixed Design of Integrated Circuits and Systems (MIXDES), Szczecin, Poland, pp. 226-229 (2004)
- H. Charlery, A. Greiner, E. Encrenaz, L. Mortiez, A. Andriahantenaina : “Using VCI in a on-chip system around SPIN network”, MIXDES Mixed Design of Integrated Circuits and Systems, Szczecin, Poland, pp. 571-576 (2004)
- M. Benabdenbi, A. Greiner, F. PĂŞcheux, E. Viaud, M. Tuna : “STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores”, DATE 2004 - Design Automation and Test in Europe Conference, Paris, France, pp. 712-713, (IEEE) (2004)
-
2003
- H. Charlery, E. Encrenaz, A. Greiner, A. Andriahantenaina, L. Mortiez : “SPIN, un micro-rĂ©seau d’interconnexion Ă commutation de paquets respectant la norme VCI. Concepts gĂ©nĂ©raux et validation.”, Symposium en Architecture et Adequation Algorithme Architecture (SympAAA 2003), La Colle sur Loup, France, pp. 337-344 (2003)
- A. Andriahantenaina, A. Greiner : “Micro-network for SoC: Implementation of a 32-port SPIN network”, Design Automation and Test in Europe Conference (DATE'2003), Munich, Germany, pp. 1128-1129, (IEEE) (2003)
- A. Andriahantenaina, H. Charlery, A. Greiner, L. Mortiez, C. Zeferino : “SPIN: a Scalable, Packet Switched, On-Chip Micro-network”, Design Automation and Test in Europe Conference (DATE'2003) Embedded Software Forum, Munich, Germany, pp. 70-73, (IEEE) (2003)
-
2002
- O. GlĂĽck, J.‑L. Lamotte, A. Greiner : “The influence of system calls and interrupts on the performance of a PC cluster using a remote DMA communication primitive”, Third International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT'2002), Kanazawa, Japan, pp. 414-421 (2002)
- V. Bourguet, M.‑M. LouĂ«rat, A. Greiner : “Composants analogiques dĂ©formables pour CAIRO+”, Troisième colloque du GDR CAO de circuits et systèmes intĂ©grĂ©s, Paris, France, pp. 25-28 (2002)
- T. Nguyen, M.‑M. LouĂ«rat, A. Greiner : “Placement Optimal d’Objets DĂ©formables dans l’Environnement de Conception Analogique CAIRO+”, Troisième Colloque du GDR CAO de circuits et systèmes intĂ©grĂ©s, Paris, France, pp. 29-32 (2002)
- G. Avot, A. Greiner, M.‑M. LouĂ«rat, K. Dioury, A. Lester, A. Debreil : “Use of MutiPhase Stability Intervals to handle Crosstalk with the Timing Analyzer hiTas”, Design Automation and Test in Europe Conference (DATE'2002), Paris, France, pp. 112-116 (2002)
- A. Andriahantenaina, A. Greiner : “Micro-rĂ©seau pour systèmes intĂ©grĂ©s : RĂ©alisation d’un rĂ©seau SPIN Ă 32 ports”, Troisième Colloque du GDR CAO de circuits et systèmes intĂ©grĂ©s, Paris, France, pp. 71-74 (2002)
- R. Buchmann, F. PĂ©trot, A. Greiner : “Pilotage Ă©vĂ©nementiel versus ordonnancement statique”, Troisième colloque du GDR CAO de circuits et systèmes intĂ©grĂ©s, Paris, France, pp. 151-154 (2002)
- B. Boutillier, L. Mortiez, A. Greiner : “Support matĂ©riel Ă l’exĂ©cution multi-threads pour le processeur Mips R3000 : Micro-Architecture et caractĂ©risation”, Troisième Colloque du GDR CAO de circuits et systèmes intĂ©grĂ©s, Paris, France, pp. 115-118 (2002)
- V. Beaudenon, A. Greiner : “Synthèse Logique utilisant un Compilateur de Cellules Complexes”, Troisième Colloque du GDR CAO de circuits et systèmes intĂ©grĂ©s, Paris, France, pp. 21-24 (2002)
- H. Charlery, A. Greiner : “Systèmes intĂ©grĂ©s : un micro-rĂ©seau d’interconnexion Ă commutation de paquets respectant la norme VCI”, Troisième colloque du GDR CAO de circuits et systèmes intĂ©grĂ©s, Paris, France, pp. 75-78 (2002)
- Ch. Alexandre, A. Greiner : “Une approche intĂ©grĂ©e pour la Synthèse-Placement-Routage des systèmes sur puce”, Troisième Colloque du GDR CAO de circuits et systèmes intĂ©grĂ©s, Paris, France, pp. 33-36 (2002)
-
2001
- M.‑M. Paget, P. Bazargan Sabet, A. Greiner : “An Example of Practice Based Engineering Education : the Design of a Microprogrammed MIPS Processor with the Alliance CAD System”, Computer Aided Learning In Engineering (CALIE'2001), Tunis, Tunisia, pp. 47-50 (2001)
- O. GlĂĽck, A. Zerrouki, J.‑L. Desbarbieux, A. Fenyö, A. Greiner, F. WajsbĂĽrt, C. Spasevski, F. Silva, E. Dreyfus : “Protocol and Performance Analysis of the MPC Parallel Computer”, 15th International Parallel and Distributed Processing Symposium (IPDPS 2001), San Francisco, CA, United States, (IEEE) (2001)
- M. Dessouky, A. Kaiser, M.‑M. LouĂ«rat, A. Greiner : “Analog Design for Reuse - Case Study : Very Low Voltage Delta-Sigma Modulators”, Design Automation and Test in Europe (DATE), Munich, Germany, pp. 353-360, (IEEE) (2001)
-
2000
- P. Guerrier, A. Greiner : “A Generic Architecture for On-chip Packet-switched Interconnections”, Design Automation and Test in Europe Conference (DATE'2000), Paris, France, pp. 250-256, (IEEE) (2000)
- K. Dioury, A. Lester, A. Debreil, G. Avot, A. Greiner, M.‑M. Rosset‑LouĂ«rat : “Hierarchical Static Timing Analysis at Bull with HiTas”, Design Automation and Test in Europe Conference User Forum (DATE'2000), Paris, France, pp. 55-60 (2000)
- A. Zerrouki, O. GlĂĽck, J.‑L. Desbarbieux, A. Fenyö, A. Greiner, C. Spasevski, F. WajsbĂĽrt, F. Silva, E. Dreyfus : “The MPC Parallel Computer : Hardware, Low-level Protocols and Performances”, Parallel and Distributed Computing and Systems (PDCS 2000), vol. 1, Las Vegas, United States, pp. 87-92 (2000)
-
1999
- M. Dessouky, A. Greiner, M.‑M. Rosset‑LouĂ«rat : “CAIRO : A hierarchical layout language for analog circuits”, Mixed Design of Integrated Circuits and Systems (MIXDES'99), Krakow, Poland, pp. 105-110 (1999)
- K. Dioury, A. Greiner, M.‑M. Rosset‑LouĂ«rat : “Hierarchical Static Timing Analysis for CMOS ULSI Circuits”, International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'99), Monterey, CA, United States, pp. 65-70 (1999)
- P. Guerrier, A. Greiner : “A Scalable Architecture for System-on-Chip Interconnections”, Sophia Antipolis Forum on MicroElectronics (SAME'99), Sophia Antipolis, France, pp. 90-93 (1999)
- F. Dromard, Y. Body, M.‑M. Paget, A. Greiner, P. Bazargan Sabet, F. PĂ©trot : “Interactive Learning of Processor Architecture”, 5th International Conference on Computer Aided Engineering Education (CAEE'99), Sofia, Bulgaria, pp. 123-129 (1999)
-
1998
- A. Lester, P. Bazargan Sabet, A. Greiner : “YAGLE, a Second generation Functional Abstractor for CMOS VLSI Circuits”, 10th International Conference on Microelectronics (ICM'98), Monastir, Tunisia, pp. 265-268, (IEEE) (1998)
- A. Lester, P. Bazargan Sabet, A. Greiner : “Circuit Disassembly for Verification and functional Abstraction of CMOS Circuits”, Sophia Antipolis forum on MicroElectronics (SAME'98), Sophia Antipolis, France, pp. 60-63 (1998)
- A. Fenyö, P. David, A. Greiner : “Noyau de communication sĂ©curisĂ© pour la machine parallèle MPC”, 10es Rencontres sur le ParallĂ©lisme (RENPAR'10), Strasbourg, France (1998)
- Y. Body, F. Dromard, A. Greiner, M.‑M. Paget, F. PĂ©trot : “SIMIPS : a cycle-precise interactive simulator for teaching microprocessor architecture”, Fourth International Conference on Computer Aided Learning and Instruction in Science and Engineering (CALISCE'98), Götborg, Sweden, pp. 146-154 (1998)
- M. Dessouky, J. Porte, A. Greiner, M.‑M. Rosset‑LouĂ«rat : “Synthèse de Circuits Analogiques CMOS”, 1ère JournĂ©e Nationale RĂ©seau Doctoral MicroĂ©lectronique, Toulouse, France (1998)
- A. Greiner, P. David, J.‑L. Desbarbieux, A. Fenyö, J.‑J. Lecler, F. Potter, V. Reibaldi, F. WajsbĂĽrt, B. Zerrouk : “La machine MPC”, Calculateurs Paralleles Reseaux et Systemes Repartis, vol. 10 (1), pp. 71-84, (La Boucle informatique) (1998)
-
1997
- F. WajsbĂĽrt, J.‑L. Desbarbieux, C. Spasevski, S. Penain, A. Greiner : “An Integrated PCI Component for IEEE 1355”, European Multimedia Microprocessor Systems and Electronic Commerce Conference and Exhibition (EMMSEC'97), Florence, Italy (1997)
- J.‑J. Lecler, A. Fenyö, A. Greiner, F. Potter : “SmartHSL : An Evaluation Board for the IEEE 1355 Technology.”, European Multimedia Microprocessor Systems and Electronic Commerce Conference and Exhibition (EMMSEC'97), Florence, Italy (1997)
- F. PĂ©trot, D. Hommais, A. Greiner : “Cycle Precise Core Based Hardware/Software System Simulation with Predictable Event Propagation”, 23rd Euromicro Conference, Budapest, Hungary, pp. 182-187, (IEEE) (1997)
- K. Dioury, A. Greiner, M.‑M. Rosset‑LouĂ«rat : “Accurate static timing analysis for deep submicronic CMOS circuits”, International Conference on Very Large Scale Integration (VLSI'97), IFIP - The International Federation for Information Processing, Gramado, Brazil, pp. 439-450, (Springer) (1997)
- I. AugĂ©, Rajesh K. Bawa, P. Guerrier, A. Greiner, L. Jacomme, F. PĂ©trot : “User Guided High Level Synthesis”, International Conference on Very Large Scale Integration (VLSI'97), IFIP - The International Federation for Information Processing, Gramado, Brazil, pp. 464-475, (Springer) (1997)
- F. PĂ©trot, D. Hommais, A. Greiner : “A Simulation Environment for Core Based Embedded Systems”, 30th Annual Simulation Symposium, Atlanta, Georgia, United States, pp. 86-91, (IEEE) (1997)
- K. Dioury, A. Greiner, M.‑M. Rosset‑LouĂ«rat : “Analyse Temporelle des Circuits VLSI Ă Haute DensitĂ© d’IntĂ©gration Utilisant des Technologies Submicroniques”, 1er Colloque CAO de Circuits IntĂ©grĂ©s et Systèmes, Grenoble, France, pp. 184-187 (1997)
- M. Dessouky, A. Greiner, M.‑M. Rosset‑LouĂ«rat : “CAIRO : Un Langage pour le Layout Analogique Symbolique”, 1er Colloque CAO de Circuits IntĂ©grĂ©s et Systèmes, Grenoble, France, pp. 14-17 (1997)
- D. Hommais, A. Greiner, F. PĂ©trot : “Un environnement de simulation pour les systèmes embarquĂ©s”, 1er Colloque CAO de Circuits IntĂ©grĂ©s et Systèmes, Grenoble, France, pp. 66-69 (1997)
- A. Lester, A. Greiner, P. Bazargan Sabet : “Un Outil d’Evaluation de la Consommation BasĂ©e sur l’Extraction d’un RĂ©seau de Portes CaractĂ©risĂ©es”, 1er Colloque CAO de Circuits IntĂ©grĂ©s et Systèmes, Grenoble, France, pp. 128-131 (1997)