AMOURI Emna
Supervision : Habib MEHREZ
Placement and routing tools to secure FPGA architectures against DPA attacks
Nowadays, most of the data computing has become digital, thereby increasing the need for security and subsequent use of cryptography. Cryptographic algorithms have traditionally been studied to withstand mathematical attacks. However, when these algorithms are implemented on electronic devices, these cryptographic systems become potential targets of attacks. One of the most dangerous attacks is the Differential Power Analysis attack which exploits the power consumption leaked by a cryptographic device to extract the secret key. The dual rail precharge logic techniques such as the WDDL method are a promising solutions to increase the robustness of secure devices against this attack. They make the circuit activity constant and uncorrelated to the processed data. Nevertheless, to guarantee the effectiveness of this approach, the routing of dual signals of the design must be carefully balanced. This thesis deals with the problem of dual signals balance in WDDL design implemented on FPGA architectures. Initially, we focus on a tree based FPGA architecture, called MFPGA. We propose and compare partitioning and placement techniques to reduce the unbalance of dual signals. Then, we propose a new Timing-Balance-Driven routing algorithm, whose goal is to balance the routing of dual signals in terms of delay propagation. Based on the Elmore delay model, results show that our new placement and routing tools have improved the delay unbalance by 93%. Besides, we target a Mesh based FPGA architecture. First, we adapt dual placement and Timing-Balance-Driven routing techniques to an island style architecture, and we obtain a gain of 90% of delay balance. Then, we propose a differential pair routing approach for a cluster based FPGA architecture. This technique achieves better results, but it has the disadvantage of depending on the characteristics of the FPGA architecture. After that, we propose a new Timing-Balance-Driven routing algorithm, which is architecture independent, and we show its efficiency in tree based and mesh based FPGAs. We note that the remaining delay unbalance in MFPGA is due to the unbalance between architecture routing wires. Finally, we target a new hierarchical FPGA architecture, called Mesh of Tree, which allows to reduce the unbalance related to the architecture. We show that we can obtain better delay balance results with the Mesh of Tree architecture, by adding to the routing algorithm a constraint which is related to the architecture characteristics.
Defence : 09/30/2011
Jury members :
M. Gilles SASSATELLI, LIRMM [Rapporteur]
M. Guy GOGNIAT, Lab-STICC [Rapporteur]
M. Jean-Claude BAJARD, UPMC
M. Laurent FESQUET, TIMA
M. Yves MATHIEU, ENST
M. Habib MEHREZ, UPMC
2008-2016 Publications
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2016
- S. Chtourou, Z. Marrakchi, E. Amouri, V. Pangracious, M. Abid, H. Mehrez : “Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 40, pp. 16-26, (Elsevier) (2016)
- S. Chtourou, M. Abid, Z. Marrakchi, E. Amouri, H. Mehrez : “The effect of interconnect depopulation on FPGA performances in terms of power, area and delay”, HPCS 2016 - International Conference on High Performance Computing & Simulation, Innsbruck, Austria, pp. 104-111, (IEEE) (2016)
- S. Chtourou, Z. Marrakchi, E. Amouri, V. Pangracious, H. Mehrez, M. Abid : “Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance”, PDP 2016 - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, Heraklion, Crete, Greece, pp. 635-642, (IEEE Computer Society) (2016)
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2015
- S. Chtourou, Z. Marrakchi, V. Pangracious, E. Amouri, H. Mehrez, M. Abid : “Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization”, ARC 2015 - 11th International Symposium on Applied Reconfigurable Computing, vol. 9040, Lecture Notes in Computer Science, Bochum, Germany, pp. 411-418, (Springer) (2015)
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2014
- A. Blanchardon, R. Chotin‑Avot, H. Mehrez, E. Amouri : “Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA”, ReConFig 2014 - International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2014)
- A. Blanchardon, R. Chotin‑Avot, H. Mehrez, E. Amouri : “Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy”, FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Munich, Germany, pp. 1-4, (IEEE) (2014)
- S.‑U. Rehman, A. Blanchardon, A. Ben Dhia, M. Benabdenbi, R. Chotin‑Avot, L. Naviner, L. Anghel, H. Mehrez, E. Amouri, Z. Marrakchi : “Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Tampa, FL, United States, pp. 553-558, (IEEE) (2014)
- V. Pangracious, E. Amouri, Z. Marrakchi, H. Mehrez : “Architecture level optimization of 3-dimensional tree-based FPGA”, Microelectronics Journal, vol. 45 (4), pp. 355-366, (Elsevier) (2014)
- S. Chtourou, M. Abid, V. Pangracious, E. Amouri, Z. Marrakchi, H. Mehrez : “Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation”, 3DIC 2014 - 2014 International 3D Systems Integration Conference, Kinsdale, Ireland, pp. 1-7, (IEEE) (2014)
- E. Amouri, Sh. Bhasin, Y. Mathieu, T. Graba, J.‑L. Danger, H. Mehrez : “Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security”, FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Munich, Germany, pp. 1-4, (IEEE) (2014)
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2013
- V. Pangracious, E. Amouri, H. Mehrez, Z. Marrakchi : “Physical Design Exploration of 3D Tree-based FPGA Architecture”, GLSVLSI'13 - The 23rd ACM international conference on Great lakes symposium on VLSI, Paris, France, pp. 335-336, (ACM) (2013)
- V. Pangracious, Z. Marrakchi, E. Amouri, H. Mehrez : “Performance analysis and optimization of high density tree-based 3d multilevel FPGA”, Reconfigurable Computing: Architectures, Tools and Applications, vol. 7806, Lecture Notes in Computer Science, Los Angeles, CA, United States, pp. 197-209, (Springer) (2013)
- E. Amouri, A. Blanchardon, R. Chotin‑Avot, H. Mehrez, Z. Marrakchi : “Efficient Multilevel Interconnect Topology for Cluster-based Mesh FPGA Architecture”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2013)
- A. Ben Dhia, S. Ur Rehman, A. Blanchardon, L. Naviner, M. Benabdenbi, R. Chotin‑Avot, H. Mehrez, E. Amouri, Z. Marrakchi : “A Defect-tolerant Cluster in a Mesh SRAM-based FPGA”, International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, pp. 434-437, (IEEE Computer Society) (2013)
- E. Amouri, H. Mehrez, Z. Marrakchi : “Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA”, International Journal of Reconfigurable Computing, vol. 2013 (802436), pp. 24, (Hindawi Publishing Corporation) (2013)
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2011
- E. Amouri : “Outils de placement et de routage pour des architectures FPGA sécurisées contre les attaques DPA”, thesis, defence 09/30/2011, supervision Mehrez, Habib (2011)
- E. Amouri, Z. Marrakchi, H. Mehrez : “Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA”, 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Montpellier, France, pp. 1-4, (IEEE) (2011)
- U. Farooq, H. Parvez, E. Amouri, H. Mehrez, Z. Marrakchi : “Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA”, International conference on Design & Technology of Integrated Systems (DTIS), Athens, Greece, pp. 1-6, (IEEE) (2011)
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2010
- E. Amouri, Z. Marrakchi, H. Mehrez : “Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA”, APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 296-299, (IEEE) (2010)
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2009
- E. Amouri, H. Mrabet, Z. Marrakchi, H. Mehrez : “Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing”, ReConFig International Conference on Reconfigurable Computing and FPGAs 2009, Cancun, Mexico, pp. 201-206, (IEEE) (2009)
- E. Amouri, H. Mrabet, Z. Marrakchi, H. Mehrez : “Placement and Routing Techniques to Improve Delay Balance of WDDL Netlist in MFPGA”, IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2009, Hammamet, Tunisia, pp. 791-794, (IEEE) (2009)
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2008
- Z. Marrakchi, H. Mrabet, E. Amouri, H. Mehrez : “Efficient Tree Topology for FPGA Interconnect Network”, GLSVLSI ACM Great Lakes Symposium on VLSI, Orlando, Florida, United States, pp. 321-326, (ACM) (2008)