FAROOQ Umer
Direção de pesquisa : Habib MEHREZ
Exploration and optimization of application specific heterogeneous tree-based fpga architectures.
Generalized and programmable nature of Field Programmable Gate Arrays (FPGAs) has made them a popular choice for the implementation of digital circuits. However, the programmability of FPGAs makes them larger, slower and more power consuming than their counterpart ASICs; hence making them unsuitable for applications requiring high density, performance and low power consumption. The main theme of this work is to improve the area of FPGAs. For this purpose, a detailed exploration and optimization of two FPGA architectures is performed: one is the well known mesh-based FPGA architecture while other is tree-based architecture that remains relatively unexplored despite its better performance and routing predictability. Further, a detailed comparison between the two architectures is also presented to highlight their respective advantages and disadvantages. The exploration and optimization of two architectures start with the introduction of heterogeneous hard-blocks in both architectures. In this work, first we present a new environment for exploration of heterogeneous tree-based FPGA architecture. This environment is flexible in nature and allows to explore different architecture techniques with varying types of hard-blocks. Further, in this work, we present an exploration environment for heterogeneous mesh-based FPGA architecture. The two environments are used to explore a number of techniques for both architectures. These techniques are later evaluated using different heterogeneous benchmarks that are placed and routed on the two architectures using a specifically developed software flow. A detailed comparison between different techniques of the two architectures is performed and results show that on average, tree-based architecture gives better overall results than mesh-based architecture. Generalized mesh and tree-based FPGA architectures are further improved by turning them into application specific FPGAs. An application specific inflexible FPGA (ASIF) is a modified FPGA with reduced flexibility and improved density. This work initially presents a new homogeneous tree-based ASIF and when compared to an equivalent tree-based FPGA, it gives 64% area gain. Further the comparison between equivalent mesh and tree-based ASIFs shows that tree-based ASIF gives 12% better area results than mesh-based ASIF. We also extend the ASIF to heterogeneous domain and experimental results show that, on average, heterogeneous tree-based ASIF gives 70% area gain when compared to equivalent heterogeneous tree-based FPGA. Further the comparison between heterogeneous mesh and tree-based ASIFs reveals that tree-based ASIF gives either equal or better results than mesh-based ASIF.
Defesas : 12/07/2011
Membros da banca :
CHILLET Daniel , IRISA, Lannion,France. (Rapporteur)
FESQUET Laurent , TIMA, Grenoble, France. (Rapporteur)
ANCEAU Francois , LIP6, Paris, France. (Examinateur)
DANGER Jean-Luc, LTCI, Paris, France. (Examinateur)
GRANADO Bertrand , ETIS, Cergy-Pontoise, France. (Examinateur)
MEHREZ Habib , LIP6, Paris, France. (Directeur de Thèse)
Publicações 2008-2018
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2018
- U. Farooq, H. Mehrez, M. Bhatti : “Inter-FPGA interconnect topologies exploration for multi-FPGA systems”, Design Automation for Embedded Systems, vol. 22 (1-2), pp. 117-140, (Springer Verlag) (2018)
- R. Chotin‑Avot, U. Farooq, M. Azeem, M. Ravoson, H. Mehrez : “Novel architectural space exploration environment for multi-FPGA based prototyping systems”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 56, pp. 169-183, (Elsevier) (2018)
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2016
- M. Azeem, R. Chotin‑Avot, U. Farooq, M. Ravoson, H. Mehrez : “Multiple FPGAs based prototyping and debugging with complete design flow”, IDT 2016 - 11th International Design & Test Symposium, Hammamet, Tunisia, pp. 171-176, (IEEE) (2016)
- U. Farooq, R. Chotin‑Avot, M. Azeem, M. Ravoson, H. Mehrez : “Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA Systems”, Rapid System Prototyping (RSP), Pittsburgh, United States, pp. 1-6 (2016)
- U. Farooq, R. Chotin‑Avot, M. Azeem, Z. Cherif, M. Ravoson, S. Khan, H. Mehrez : “Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration”, Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, pp. 641-645, (IEEE) (2016)
- U. Farooq, M. Faisal Aslam : “Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA”, Journal of King Saud University - Computer and Information Sciences, (Elsevier) (2016)
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2014
- V. Pangracious, Z. Marrakchi, N. Beltaief, H. Mehrez, U. Farooq : “Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA”, DTIS 2014 - 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini, Greece, pp. 1-6, (IEEE) (2014)
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2013
- V. Pangracious, H. Mehrez, U. Farooq, Z. Marrakchi : “High Performance 3-Dimensional Heterogeneous Tree-based FPGA Architectures (HT-FPGA)”, FPGAworld'13 - The 10th FPGAworld Conference, Stockholm, Sweden, pp. 3:1-3:6, (ACM) (2013)
- V. Pangracious, H. Mehrez, N. Beltaief, Z. Marrakchi, U. Farooq : “Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2013)
- U. Farooq, H. Parvez, H. Mehrez, Z. Marrakchi : “Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA”, Microelectronics Journal, vol. 44 (12), pp. 1052-1062, (Elsevier) (2013)
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2012
- U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “A New Heterogeneous Tree-based Application Specific FPGA and Its Comparison with Mesh-based Application Specific FPGA”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 36 (8), pp. 588-605, (Elsevier) (2012)
- U. Farooq, Z. Marrakchi, H. Mehrez : “Tree Based Heterogeneous FPGA Architectures, Application Specific Exploration and Optimization”, (Springer), (ISBN: 978-1-4614-3593-8) (2012)
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2011
- U. Farooq : “Exploration and optimization of application specific heterogeneous tree-based fpga architectures”, tese, defesas 12/07/2011, direção de pesquisa Mehrez, Habib (2011)
- U. Farooq, H. Parvez, E. Amouri, H. Mehrez, Z. Marrakchi : “Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA”, International conference on Design & Technology of Integrated Systems (DTIS), Athens, Greece, pp. 1-6, (IEEE) (2011)
- U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA”, The 7th International Symposium on Applied Reconfigurable Computing, vol. 6578, Lecture Notes in Computer Science, Belfast, United Kingdom, pp. 218-229, (Springer) (2011)
- U. Farooq, H. Parvez, H. Mehrez, Z. Marrakchi : “Exploration of Heterogeneous FPGA Arcrchitectures”, International Journal of Reconfigurable Computing, vol. 2011, pp. 121404, (Hindawi Publishing Corporation) (2011)
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2010
- U. Farooq, Z. Marrakchi, H. Mehrez : “A New Datapath-Oriented Tree-based FPGA Architecture”, IEEE International Conference on Microelectronics (ICM), Cairo, Egypt, pp. 403-406, (IEEE) (2010)
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2009
- Z. Marrakchi, U. Farooq, H. Mrabet, H. Mehrez : “Comparison of Tree-Based and Mesh-Based Coarse-Grained FPGA Architectures”, ICM International Conference on Microelectronics, Marrakech, Morocco, pp. 248-251, (IEEE) (2009)
- U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “A New Tree-based coarse-grained FPGA Architecture”, IEEE International Conference on PhD. Research in MicroElectronics, PRIME'09, Cork, Ireland, pp. 48-51, (IEEE) (2009)
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2008
- H. Parvez, Z. Marrakchi, U. Farooq, H. Mehrez : “A New Coarse-grained FPGA Architecture Exploration Environment”, ICFPT International Conference on Field-Programmable Technology, Taipei, Taiwan, Province of China, pp. 285-288, (IEEE) (2008)
- U. Farooq, Z. Marrakchi, H. Mrabet, H. Mehrez : “The Effect of LUT and Cluster Size on a Tree based FPGA Architecture”, ReConFig International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 115-120, (IEEE) (2008)