رئاسـة البـحث : Habib MEHREZ

Architecture d'un système hétérogène pour la reconnaissance de formes

إصدارات 1997-2000

• 2000
  • M. Aberbour, H. Mehrez, F. Durbin, J. Haussy, P. Lalande, A. Tissot : “A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology”, CAMP 2000 - Fifth International Workshop on Computer Architectures for Machine Perception, Padova, Italy, pp. 155-162, (IEEE Computer Society) (2000)
• 1999
  • M. Aberbour : “Architecture d’un système hétérogène pour la reconnaissance de formes”, أطروحة, مناقـشـة مـذكـرة 29/09/1999, رئاسـة البـحث Mehrez, Habib (1999)
• 1998
  • M. Aberbour, H. Mehrez, F. Durbin, Th. Garié, A. Tissot : “System Level Design of a Pattern Recognition System Based on the Gabor Wavelets”, IEEE-SP Conference on Time-Frequency Time-Scale Analysis (TFTS'98), Pittsburgh, PA, United States, pp. 237-240, (IEEE) (1998)
  • M. Aberbour, H. Mehrez, F. Durbin, Th. Garié, A. Tissot : “Algorithms and VLSI Architectures for Pattern Recognition Based on the Gabor Wavelets”, International Conference on Signal Processing Applications and Technology (ICSPAT'98), Toronto, Canada, pp. 1455-1459 (1998)
  • M. Aberbour, H. Mehrez : “Architecture and design Methodology of the RBF-DDA Neural Network”, IEEE International Symposium on Circuits and Systems (ISCAS'98), vol. 3, Monterey, CA, United States, pp. 199-202, (IEEE) (1998)
  • M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher, A. Guyot : “On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6 (1), pp. 114-121, (IEEE) (1998)
• 1997
  • A. Guyot, S.‑J. Abou‑Samra, M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher : “Modelling and synthesis of optimal adders under left-to-right input arrival”, IFIP International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, France, (IFIP) (1997)
  • M. Aberbour, F. Ahmad, H. Mehrez : “A Hardware Implementation of an RBF Neural Network : Architecture and Design Methodology”, International Conference on Signal Processing and Technology 97, vol. 3, San Diego, CA, United States, pp. 199-202 (1997)
  • M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher, A. Guyot : “A time driven adder generator architecture”, 9^th IFIP International Conference on Very Large Scale Integration (VLSI'97), Gramado, RS, Brazil, pp. 453-463, (Springer) (1997)
  • M. Aberbour, A. Derieux, H. Mehrez, N. Vaucher : “Teaching the design of a chip under the Cadence Opus environment using the Alliance cell libraries”, MSE '97 - IEEE International Conference on Microelectronic Systems Education, Arlington, VA, United States, pp. 81-82, (IEEE Computer Society) (1997)