Direção de pesquisa : Roselyne CHOTIN, Lionel LACASSAGNE

Design space exploration of image processing algorithms on FPGAs

Implementing image processing algorithms for embedded devices is a scientific topic of great importance and many researchers focus their work on this domain. Many trade-offs have to be made in order to fit these algorithms in a specific embedded device and at the same time achieve real time computation and acceptable algorithmic precision. In this thesis, we focus on the design space exploration of an optical flow algorithm called Multi-scale Horn and Schunck algorithm in an Arria 10 FPGA. Although we focus on a specific algorithm and a specific device, the exploration we perform and the propositions of this thesis can also be applied to other algorithms and FPGA devices too.
The first thing we explore is the accuracy of the design. We use smaller floating point formats and we tune different parameters of the algorithm in order to increase the accuracy of the design and at the same time provide an implementation which achieves real time computation. We explore different interpolation algorithms as well as different iteration factors. As this algorithm is a multi-rate image processing algorithm, we propose solutions in order to tackle this nature of the algorithm and increase computation throughput. We use pipeline and vectorized architectures in order to further increase the computation speed and we introduce trans-floating computation which enables us to fit more processing elements in our architectures. We explore how all these solutions affect the resources usage of the FPGA, such as the LUTs, DSPs and Block RAMs utilization. Furthermore, we propose approaches in order to overcome the bottleneck of the external memory bandwidth.
Following that, and by taking into account all our propositions, we perform a design space exploration of the algorithm, which helps the optical flow designer choose among different configurations according to the constraints of the project. We compare our designs with other state of the art works in FPGAs and we show that our fastest design achieves the highest throughput compared to all the rest single FPGA optical flow designs to the best of our knowledge. At the same time our implementations achieve comparable accuracy of detection and less hardware utilization.

Publicações 2020-2023

• 2023
  • I. Bournias : “Design space exploration of image processing algorithms on FPGAs”, tese, defesas 02/06/2023, direção de pesquisa Chotin, Roselyne Lacassagne, Lionel (2023)
• 2022
  • I. Bournias, R. Chotin, L. Lacassagne : “Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs”, IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, United States (2022)
• 2021
  • I. Bournias, R. Chotin, L. Lacassagne : “FPGA Acceleration of the Horn and Schunck Hierarchical algorithm”, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, Republic of, (IEEE) (2021)
  • D. Genius, I. Bournias, L. Apvrille, R. Chotin : “Model-Based Virtual Prototyping of CPS: Application to Bio-Medical Devices”, International Conference on Model-Driven Engineering and Software Development, vol. 1361, CCIS, Valletta, Malta, pp. 74-96, (Springer, Cham) (2021)
• 2020
  • F. Pêcheux, L. Andrade Porras, M.‑M. Louërat, I. Bournias, R. Chotin, D. Genius : “Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions”, 2020 Forum for Specification and Design Languages (FDL), Kiel, Germany, pp. 1-8, (IEEE) (2020)
  • D. Genius, I. Bournias, L. Apvrille, R. Chotin : “High-level Partitioning and Design Space Exploration for Cyber Physical Systems”, Proceedings of the 8^th International Conference on Model-Driven Engineering and Software Development - Volume 1: MODELSWARD, Valletta, Malta, pp. 84-91, (SCITEPRESS) (2020)