ALI EL SAYED Sarah

Dottore di ricerca
Gruppo di ricerca : CIAN
Data di partenza : 03/31/2022
https://lip6.fr/Sarah.ElSayed

Relatore : Haralampos STRATIGOPOULOS

Fault Tolerance in Hardware Spiking Neural Networks

Artificial Intelligence (AI) and machine learning algorithms are taking up the lion's share of the technology market nowadays, and hardware AI accelerators are foreseen to play an increasing role in numerous applications, many of which are mission-critical and safety-critical. This requires assessing their reliability and developing cost-effective fault tolerance techniques; an issue that remains largely unexplored for neuromorphic chips and Spiking Neural Networks (SNNs).
A tacit assumption is often made that reliability and error-resiliency in Artificial Neural Networks (ANNs) are inherently achieved thanks to the high parallelism, structural redundancy, and the resemblance to their biological counterparts. However, prior work in the literature unraveled the falsity of this assumption and exposed the vulnerability of ANNs to faults. This requires assessing their reliability and developing cost-effective fault tolerance techniques; an issue that remains largely unexplored for neuromorphic chips and Spiking Neural Networks (SNNs). In this thesis, we tackle the subject of testing and fault tolerance in hardware SNNs. We start by addressing the issue of post-manufacturing test and behavior-oriented self-test of hardware neurons. Then we move on towards a global solution for the acceleration of testing and resiliency analysis of SNNs against hardware-level faults. We also propose a neuron fault tolerance strategy for SNNs, optimized for low area and power overhead.
Finally, we present a hardware case-study which would be used as a platform for demonstrating fault-injection experiments and fault-tolerance capabilities.

Difesa : 10/28/2021

Membri della commissione :

BOSIO Alberto (INL, Ecole Centrale de Lyon) [Rapporteur]
SANCHEZ Ernesto (Politecnico di Torino) [Rapporteur]
SENTIEYS Olivier (INRIA, Université de Rennes)
ALOUANI Ihsen (IEMN, UPolytech HF)
VATAJELU Ioana (CNRS, TIMA, Université de Grenoble-Alpes)
CAMUNAS-MESA Luis (IMSE, Universidad de Sevilla)
STRATIGOPOULOS Haralampos (CNRS, LIP6/ Sorbonne Université)

Data di partenza : 03/31/2022

Pubblicazioni 2019-2023

  • 2023
  • 2022
  • 2021
  • 2020
    • S. El‑Sayed, Th. Spyrou, A. Pavlidis, E. Afacan, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Spiking Neuron Hardware-Level Fault Modeling”, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), Naples, Italy (2020)
  • 2019
    • S. Ali El‑Sayed, L. Camuñas‑Mesa, B. Linares‑Barranco, Haralampos‑G. Stratigopoulos : “Self-Testing Analog Spiking Neuron Circuit”, 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2019), Lausanne, Switzerland, pp. 81-84, (IEEE) (2019)
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