BRIÈRE Alexandre

وحـدة : SYEL
تحديد : Jussieu
    UPMC - LIP6
    Boîte courrier 169
    Couloir 24-25, Étage 5, Bureau 513
    4 place Jussieu
    75252 PARIS CEDEX 05
Tel: +33 1 44 27 75 07, Alexandre.Briere (at)
رئاسـة البـحث : François PÊCHEUX
تأطـير مـشـترك : DENOULET Julien

Modélisation système d’une architecture d’interconnexion RF reconfigurable pour les many-cœurs

The growing number of cores in a single chip goes along with an increase in communications. The variety of applications running on the chip causes spatial and temporal heterogeneity of communications. To address these issues, we present in this thesis a dynamically reconfigurable interconnect based on Radio Frequency (RF) for intra chip communications. The use of RF allows to increase the bandwidth while minimizing the latency. Dynamic reconfiguration of the interconnect allows to handle the heterogeneity of communications. We present the rationale for choosing RF over optics and 3D, the detailed architecture of the network and the chip implementing it, the evaluation of its feasibility and its performances. During the evaluation phase we were able to show that for a CMP of 1 024 tiles, our solution allowed a performance gain of 13 %. One advantage of this RF interconnect is the ability to broadcast without additional cost compared to point-to-point communications, opening new perspectives in terms of cache coherence.
مناقـشـة مـذكـرة : 08/12/2017 - 14h - Site Jussieu Atrium Grande salle de visioconférence
أعـضاء لجنة المناقـشة :
Dr Fabien Clermidy - CEA - Grenoble [Rapporteur]
Dr Gilles Sassatelli - LIRMM - Montpellier [Rapporteur]
Dr Roselyne Chotin-Avot - UPMC - Paris
Pr Philippe Coussy - UBS - Lorient
Pr Lionel Lacassagne - UPMC - Paris
Pr Ian O’Connor - ECL - Lyon
Dr Julien Denoulet - UPMC - Paris
Pr François Pêcheux - UPMC - Paris
Current position : Enseignant chercheur - ESIEA

إصدارات 2014-2017

 Mentions légales
| خـريـطـة المـوقـع