责任导师 : François ANCEAU

助理责任导师 : GALAYKO Dimitri

Distributed Clock Generation for Large Synchronous SOCs.

This thesis addresses the problem of global synchronization in large system on chip (SoC). It focuses on the study of an alternative clock generation technique to conventional clock distribution and asynchronous communication. It allows implementation of highly reliable synchronous circuit.
My PhD project aims to study and implement a large network (10x10) of all digital phase-locked loop (ADPLL), containing 100 nodes generating a clock for each local digital circuitry. Several prototypes were designed, modeled and tested, including one implemented in 65nm CMOS technlogy, generating clocks in the range 903-1161 MHz. It highlights a maximum phase error of less than 40 ps between two clocks in any neighboring zones.
In order to validate the performance of synchronization in ASIC, we designed an on-chip clocking error measurement circuit. This circuit has a low rate for the off-chip readout (several MHz), and a high resolution (+-2 ps).

2011-2019 刊物