GUTHMULLER Eric
Direção de pesquisa : Alain GREINER
Co-supervisão£o : MIRO-PANADES Ivan
Adaptive cache architecture exploiting 3D stacking technologies in a manycore context
The parallelization of processors has led to a increased need of external memory bandwidth. As the number of cores grows, it becomes difficult to embed enough memory caches next to processors. The appearance of 3D stacking technologies makes the stacking of memory on top of processors possible.
In this thesis, we propose a 3D cache architecture for manycore exploiting 3D stacking technologies to surpass the limitations of existing architectures. This architecture consists of a regular mesh of cache tiles interconnected by 3D networks on chip and form a non uniform distributed cache. This 3D cache is reusable in a lot of contexts in order to reduce the production cost and also adapts itself to the needs of the application running on the processing architecture. At last, this 3D cache is tolerant to permanent faults to reduce the manufacturing cost and lengthen the lifetime of the circuit.
We have evaluated the efficiency of adaptive mecanisms implanted in the architecture and showed that these mecanisms improve its efficiency. We have also compared our architecture to the WideIO standard and showed that our architecture performs best both in terms of bandwidth and energy efficiency. At last, we have done its hardware implementation in a 28 nm CMOS process. This hardware implementation has been taken up to the drawing of masks to evaluate the properties of our architecture.
Defesas : 11/04/2013
Membros da banca :
Frédéric Pétrot: Professeur, Laboratoire TIMA - Grenoble [Rapporteur]
Olivier Sentieys: Professeur, IRISA/ENSSAT - Rennes [Rapporteur]
Jean-Claude Bajard: Professeur, Université Pierre et Marie Curie - Paris
Eric Flamand: Ingénieur, STMicroelectronics - Grenoble
Guy Gogniat: Professeur, Université de Bretagne-Sud - Lorient
Alain Greiner: Professeur, Université Pierre et Marie Curie - Paris
Ivan Miro-Panades: Docteur, CEA-Leti - Grenoble
Publicações 2012-2021
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2021
- P. VIVET, E. Guthmuller, Y. Thonnart, G. Pillonnet, C. Fuguet, I. Miro‑Panades, G. Moritz, J. Durupt, Ch. Bernard, D. Varreau, J. Pontes, S. Thuries, D. Coriat, M. Harrand, D. Dutoit, D. Lattard, L. Arnaud, J. Charbonnier, P. Coudrain, A. Garnier, F. Berger, A. Gueugnot, A. Greiner, Q. Meunier, A. Farcy, A. Arriordaz, S. Chéramy, F. Clermidy : “IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management”, IEEE Journal of Solid-State Circuits, vol. 56 (1), pp. 79-97, (Institute of Electrical and Electronics Engineers) (2021)
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2020
- P. VIVET, E. Guthmuller, Y. Thonnart, G. Pillonnet, G. Moritz, I. Miro‑Panades, C. Fuguet, J. Durupt, Ch. Bernard, D. Varreau, J. Pontes, S. Thuries, D. Coriat, M. Harrand, D. Dutoit, D. Lattard, L. Arnaud, J. Charbonnier, P. Coudrain, A. Garnier, F. Berger, A. Gueugnot, A. Greiner, Quentin L. Meunier, A. Farcy, A. Arriordaz, S. Chéramy, F. Clermidy : “A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters”, 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, United States, pp. 46-48, (IEEE) (2020)
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2018
- E. Guthmuller, C. Fuguet, P. Vivet, C. Bernard, I. Miro‑Panades, J. Durupt, E. Beigne, D. Lattard, S. Cheramy, A. Greiner, Quentin L. Meunier, P. Bazargan Sabet : “A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches”, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Dresden, Germany, pp. 318-321, (IEEE) (2018)
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2013
- E. Guthmuller : “Architecture adaptative de mémoire cache exploitant les techniques d’empilement tridimensionnel dans le contexte des multiprocesseurs intégrés sur puce”, tese, defesas 11/04/2013, direção de pesquisa Greiner, Alain, co-supervisão£o : Miro-panades, Ivan (2013)
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2012
- E. Guthmuller, I. Miro‑Panades, A. Greiner : “Adaptive Stackable 3D Cache Architecture for Manycores”, VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on, Amherst, MA, United States, pp. 39-44 (2012)