LIP6 1998/036
- Thesis
Une méthode de tes des circuits intégrés, basée sur un découpage structurel peu recouvrant - O. Florent
- 148 pages - 07/09/1998- document en - http://www.lip6.fr/lip6/reports/1998/lip6.1998.036.ps.gz - 290 Ko
- Contact : Olivier.florent (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : VLSI testing, Boundary-scan, built-in self-test, design reuse, automatic partitioning, ATPG tool, distribution
- Publisher : Francois.Dromard (at) nulllip6.fr
Our study presents a "divide and conquer" strategy for digital circuit testing, in order to generate deterministic patterns using classical ATPG tools. Today's integrated circuits have scan-paths, some are using built-in self-test or macro-cells, and almost all have a Boundary-Scan architecture. Unfortunately, design reuse and heterogeneous libraries do not allow designers to choose the style and the location of the test structures. We propose a splitting process which constructs overlapping testable units around the test structures. Theses testable units can be processed independently by ATPG tools across a network of workstations.
The boundaries of the testable units are the observable and controllable signals of the structural flattened view of the circuit. We identify automatically these signals, using logical and symbolic simulations. Next the circuit is split in testable units, and the overlap factor due to this splitting process is minimized. Gates from Boundary-scan logic, or gates from area with built-in self test are not included in testable units. We can now obtain test vectors and a fault dictionary for each testable unit using a classic ATPG tool.
We merge all the test vectors and the fault dictionaries to obtain one global test sequence and one global fault dictionary for the circuit. Test vectors from testable units are run in parallel to save test length.
A set of tools based on our test method has been realized in the framework of the ALLIANCE CAD system, using HITEST, a commercial product, as the APTG tool. With these tools, we have been able to process a real circuit which integrates macro-cells.
The boundaries of the testable units are the observable and controllable signals of the structural flattened view of the circuit. We identify automatically these signals, using logical and symbolic simulations. Next the circuit is split in testable units, and the overlap factor due to this splitting process is minimized. Gates from Boundary-scan logic, or gates from area with built-in self test are not included in testable units. We can now obtain test vectors and a fault dictionary for each testable unit using a classic ATPG tool.
We merge all the test vectors and the fault dictionaries to obtain one global test sequence and one global fault dictionary for the circuit. Test vectors from testable units are run in parallel to save test length.
A set of tools based on our test method has been realized in the framework of the ALLIANCE CAD system, using HITEST, a commercial product, as the APTG tool. With these tools, we have been able to process a real circuit which integrates macro-cells.