LIP6 1997/040
- Thesis
Une nouvelle méthode de simulation par évaluation directe des expressions logiques représentées par des graphes : application à des circuits modélisés par un sous-ensemble du langage VHDL - H. N. Vuong
- 118 pages - 01/07/1998- document en - http://www.lip6.fr/lip6/reports/1997/lip6.1997.040.ps.gz - 978 Ko
- Contact : huu-nghia.vuong (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : Logical Simulation, Booleans Networks, VHDL, Alliance, Graphs, Event-driven
- Publisher : Francois.Dromard (at) nulllip6.fr
We present in this thesis, a simulation method for integrated circuits based on direct evaluation of logical expressions represented by graphs (BDD and Lisp Like Trees). The circuits are described with data structures. We use a VHDL subset that excludes processes and timing information. This subset has been defined in order to be accepted by the tools of the Alliance VLSI CAD System that handle behavioural information (logic synthesis, formal proof, functional abstraction). This subset has been used with success in research projects dealing with high complexity circuits. The event-driven simulation technique has been used in an Alliance tool prototype called Asimut. The result of the comparison of this prototype versus industrials simulators (Cadence and Synopsys) shows than we obtain acceptables performances. This prototype allowed us to adjust a software patform aimed at helping the development of tools that need an event-driven simulation kernel.