LIP6 1997/023
- Thesis
Etude et réalisation d'une liaison série a un gigabaud indépendante du codage - A. Pierre Duplessix
- 102 pages - 10/15/1997- document en - http://www.lip6.fr/lip6/reports/1997/lip6.1997.023.ps.gz - 3,498 Ko
- Contact : anne.pierreduplessix (at) nullst.com
- Ancien Thème : ASIM
- Keywords : Serial link - Delay locked loop - Gigabit transmission - HS Link - Variable delay
- Publisher : Francois.Dromard (at) nulllip6.fr
Switching from a parallel interface to a serial interface would significantly increase the input and output flows of integrated circuits. To achieve this, one can integrate several serial links on the chip peripheral buffer ring. A serial link contains a parallel to serial transformer (serialiser) and a serial to parallel transformer (deserialiser). Parallel architecture, network structures and multimedia applications would largely benefit from the use of high speed serial links.
The subject of this study is designing a high speed serial link which can take as an input any type of coded data and which can transmit on two medias: optical cable or coaxial electrical cable. Our aim is to provide a macrocell with the following characteristics: small silicon area, reduced power consumption, easily implemented into a CMOS chip. The document describes the original principles that were put into shape to achieve parallel to serial and serial to parallel transformations. It also presents the results obtained by implementing those principles on a test chip.
The subject of this study is designing a high speed serial link which can take as an input any type of coded data and which can transmit on two medias: optical cable or coaxial electrical cable. Our aim is to provide a macrocell with the following characteristics: small silicon area, reduced power consumption, easily implemented into a CMOS chip. The document describes the original principles that were put into shape to achieve parallel to serial and serial to parallel transformations. It also presents the results obtained by implementing those principles on a test chip.