LIP6 2001/005
- Thesis
Etude, conception et caractérisation de mémoires CMOS , faible consommation, faible tension en technologies submicroniques - A. Turier
- 110 pages - 12/13/2001- document en - http://www.lip6.fr/lip6/reports/2001/lip6.2001.005.pdf - 1,617 Ko
- Contact : arnaud.turier (at) nullieee.org
- Ancien Thème : ASIM
- Keywords : low-power, low-voltage, embedded memories, ROM, SRAM, leakage currents, memory modeling, memory compiler
- Publisher : Francois.Dromard (at) nulllip6.fr
In just a few years, low power consumption has become one of the greatest stakes in microelectronics in part thanks to the rise of portable electronic devices such as pagers, cellular phones, computers and medical equipment, all aimed at general public. Today's trend, System On Chip, leads circuit designers to gather as many different kinds of components as possible, memories for instance, on one and same chip. Today, memories take up much of the circuit's area and total power consumption. Also, to reduce memory power consumption will help reduce all of the circuit power consumption. In this dissertation, we present a ROM architecture for low-power consumption applications. This architecture has been validated on silicon using 0.5um and 0.35um technologies for instances of different sizes. We also show how to optimize the power consumption of a SRAM without increasing the timings. With device reduction and power supply lowering, leakage currents hold a more and more prominent place in memory power consumption. We explain how to characterize leakage currents and we present a method to reduce them, in ROMs for example. As for large capacity memories, we faced the problem of their electrical simulation. This is why we suggest a method based on current generators so as to model the redundant parts found in the memories. Finally, we show the development and design of a ROM compiler that uses the architecture that was previously presented. We present the problems linked to design and validation flow as well as their keys.